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MIOInterface
MIO 0...12QSPI Flash Memory
MIO 20...21I2C 1
MIO 22...23UART 0
MIO 26...37GEM 0
MIO 46...51SD 1
MIO 52...63USB 0
MIO 64...75USB 1
MIO 76...77MDIO 0

System Controller

System controller chip is Intel MAX10 10M08SAU169C8G Chip with board control firmware.

DDR4 SODIMM Socket

The Zynq UltraScale+ DDRC hard memory controller is wired to the DDR4 SODIMM Socket U3. 

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This interface connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.

FT601Q SignalFPGA Pin
FIFO_CLK
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See FT600Q-FT601Q IC Datasheet for interface details.

Backplane USB Interface

Zynq UltraScale+ USB controller connected to backplane connector J1C via USB PHY chip U11.

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MGT reference clocks are connected to banks 129, 229 and 505. Banks 128 and 130 should share clock from bank 129, banks 230 and 228 from bank 229.

DIP-Switches

S1

SwitchDescription
1Boot Mode 0
2Boot Mode 1
3Boot Mode 2
4Boot Mode 3

See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description. Most common modes are

Boot ModeSW1:4SW1:3SW1:2SW1:1
JTAG Boot ModeONONONON
Quad-SPIONONONOFF
SD CardONONOFFOFF

S2

SwitchDescription
1SC JTAGEN
2EEPROM WP (Write protect)
3FPGA PUDC
4SC Switch (Reserved for future use)


LEDs

LEDSignalChipPinDescription
Front panel LED 1 (Red)LED_FP_1FPGA U1AF15PL User defined LED
Front panel LED 2 (Green)LED_FP_2FPGA U1AG15PL User defined LED
Front panel LED 3 (Green)LED_FP_3FPGA U1AE15PL User defined LED
Front panel LED 4 (Green)LED_FP_4SC U18M4Power Good


Clocking

draw.io Diagram
bordertrue
viewerToolbartrue
fitWindowfalse
diagramNameClocks Diagram
simpleViewerfalse
width
diagramWidth641
revision2

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