Page History
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MIO | Interface |
---|---|
MIO 0...12 | QSPI Flash Memory |
MIO 20...21 | I2C 1 |
MIO 22...23 | UART 0 |
MIO 26...37 | GEM 0 |
MIO 46...51 | SD 1 |
MIO 52...63 | USB 0 |
MIO 64...75 | USB 1 |
MIO 76...77 | MDIO 0 |
System Controller
System controller chip is Intel MAX10 10M08SAU169C8G Chip with board control firmware.
DDR4 SODIMM Socket
The Zynq UltraScale+ DDRC hard memory controller is wired to the DDR4 SODIMM Socket U3.
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This interface connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.
FT601Q Signal | FPGA Pin |
---|---|
FIFO_CLK | |
... |
See FT600Q-FT601Q IC Datasheet for interface details.
Backplane USB Interface
Zynq UltraScale+ USB controller connected to backplane connector J1C via USB PHY chip U11.
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MGT reference clocks are connected to banks 129, 229 and 505. Banks 128 and 130 should share clock from bank 129, banks 230 and 228 from bank 229.
DIP-Switches
S1
Switch | Description |
---|---|
1 | Boot Mode 0 |
2 | Boot Mode 1 |
3 | Boot Mode 2 |
4 | Boot Mode 3 |
See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description. Most common modes are
Boot Mode | SW1:4 | SW1:3 | SW1:2 | SW1:1 |
---|---|---|---|---|
JTAG Boot Mode | ON | ON | ON | ON |
Quad-SPI | ON | ON | ON | OFF |
SD Card | ON | ON | OFF | OFF |
S2
Switch | Description |
---|---|
1 | SC JTAGEN |
2 | EEPROM WP (Write protect) |
3 | FPGA PUDC |
4 | SC Switch (Reserved for future use) |
LEDs
LED | Signal | Chip | Pin | Description |
---|---|---|---|---|
Front panel LED 1 (Red) | LED_FP_1 | FPGA U1 | AF15 | PL User defined LED |
Front panel LED 2 (Green) | LED_FP_2 | FPGA U1 | AG15 | PL User defined LED |
Front panel LED 3 (Green) | LED_FP_3 | FPGA U1 | AE15 | PL User defined LED |
Front panel LED 4 (Green) | LED_FP_4 | SC U18 | M4 | Power Good |
Clocking
draw.io Diagram | ||||||||||||||||||
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Overview
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