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Table of Contents
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Overview
The Trenz Electronic TEC0850 is an industrial-grade MPSoC SoM integrating a Xilinx Zynq UltraScale+ MPSoC, with 64-bit wide SODIMM DDR4 SDRAM, max. Dual 512 MByte Flash memory for configuration and operation. 24 Gigabit transceivers on PL side and 4 PS side. Powerful switch-mode power supplies for all onboard voltages. A large number of configurable I/Os. 3U form factor.
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Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.
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Key Features
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Board Component Descriptions
Zynq UltraScale XCZU15EG MPSoC
The TEC0850 board is populated with the Zynq UltraScale+ XCZU15EG-1FFVB1156E MPSoC.
I/O Interfaces
Main IO interfaces are shown on the image below.
Block Diagram
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PS MIO Configuration
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System Controller
System controller chip is Intel MAX10 10M08SAU169C8G Chip with board control firmware.
DDR4 SODIMM Socket
The Zynq UltraScale+ DDRC hard memory controller is wired to the DDR4 SODIMM Socket U3.
Quad-SPI Flash Memory
Board has two N25Q512A11G1240E connected in a dual parallel mode.
I2C
The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.
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UART and JTAG
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Main Components
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Initial Delivery State
Storage device name | Content | Notes |
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Boot Process
Signals, Interfaces and Pins
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USB-C
Front panel USB-C Interface connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.
FT601Q Signal | FPGA Pin |
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FIFO_CLK | |
... |
See FT600Q-FT601Q IC Datasheet for interface details.
MicroUSB
Front panel Micro-USB Interface provides access to UART and JTAG functions via Board has USB-UART bridge based on FTDI FT2232 chip. Use of this feature requires that USB driver is installed on your host PC. UART0 with MIO 22 .. 23 should be selected in "Zynq UltraScale+ MPSoC" configuration.
The Digilent plug-in software and cable drivers must be installed on your machine for you to be able to use JTAG interface.
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Ethernet
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SD
There are some limitations to use SD card Interface in Linux.
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To force Linux driver not to use this features add following instructions to device tree file. &sdhci1 { no-1-8-v; |
USB
Board has 3 USB interfaces.
Front panel Micro-USB Interface
This interface provides access to UART and JTAG functions via FTDI FT2232 chip.
Front panel USB-C Interface
This interface connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.
...
See FT600Q-FT601Q IC Datasheet for interface details.
Backplane USB Interface
Zynq UltraScale+ USB controller connected to backplane connector J1C via USB PHY chip U11.
DACs
RJ45 -Ethernet
cPCIe
...Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate.
MGT
The TEC0850 board has 30 MGT lines routed to backplane connectors.
Bank | Connector | Lanes |
---|---|---|
PL 128 | J4G and J4H | 4 |
PL 129 | J5A and J5B | 4 |
PL 130 | J5C and J5D | 4 |
PL 230 | J4G and J4H | 4 |
PL 229 | J5A and J5B | 4 |
PL 228 | J5C and J5D | 4 |
PS 505 | J1A | 4 |
MGT reference clocks are connected to banks 129, 229 and 505. Banks 128 and 130 should share clock from bank 129, banks 230 and 228 from bank 229.
USB Interface
Zynq UltraScale+ USB controller connected to backplane connector J1C via USB PHY chip U11.
DDR4 SODIMM Socket
The Zynq UltraScale+ DDRC hard memory controller is wired to the DDR4 SODIMM Socket U3.
Circular Push Pull Connector
PicoBlade Connector
Pin Heater 2,54mm (2x5)
Battery holder
On-board Peripherals
Zynq UltraScale XCZU15EG MPSoC
The TEC0850 board is populated with the Zynq UltraScale+ XCZU15EG-1FFVB1156E MPSoC.
Main IO interfaces are shown on the image below.
PS MIO Configuration
MIO | Interface |
---|---|
MIO 0...12 | QSPI Flash Memory |
MIO 20...21 | I2C 1 |
MIO 22...23 | UART 0 |
MIO 26...37 | GEM 0 |
MIO 46...51 | SD 1 |
MIO 52...63 | USB 0 |
MIO 64...75 | USB 1 |
MIO 76...77 | MDIO 0 |
Table 10: Default MIO Configuration
MAX10 System Controller
System controller chip is Intel MAX10 10M08SAU169C8G Chip with board control firmware.
FTDIs
FT2232H
FT601Q-B-T
Quad-SPI Flash Memory
Board has two N25Q512A11G1240E connected in a dual parallel mode.
EEPROMs
I2C
The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.
I2C address | Chip | Description |
---|---|---|
0x50 | U63 24AA128T-I/ST | 128K Serial EEPROM |
0x53 | U64 24AA025E48T-I/OT | 2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity |
USB PHY
Gigabit Ethernet PHY
Board has Marvell Alaska 88E1512 Ethernet PHY which use MDIO address 1.
8Bit DACs
Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate.
DIP-Switches
S1
Switch | Description |
---|---|
1 | Boot Mode 0 |
2 | Boot Mode 1 |
3 | Boot Mode 2 |
4 | Boot Mode 3 |
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Boot Mode | SW1:4 | SW1:3 | SW1:2 | SW1:1 |
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JTAG Boot Mode | ON | ON | ON | ON |
Quad-SPI | ON | ON | ON | OFF |
SD Card | ON | ON | OFF | OFF |
S2
Switch | Description |
---|---|
1 | SC JTAGEN |
2 | EEPROM WP (Write protect) |
3 | FPGA PUDC |
4 | SC Switch (Reserved for future use) |
Buttons
LEDs
LED | Signal | Chip | Pin | Description |
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Front panel LED 1 (Red) | LED_FP_1 | FPGA U1 | AF15 | PL User defined LED |
Front panel LED 2 (Green) | LED_FP_2 | FPGA U1 | AG15 | PL User defined LED |
Front panel LED 3 (Green) | LED_FP_3 | FPGA U1 | AE15 | PL User defined LED |
Front panel LED 4 (Green) | LED_FP_4 | SC U18 | M4 | Power Good |
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Programmable Clock Generators
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I2C
The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.
I2C address | Chip | Description |
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0x69 | U14 Si5345 | Clock generator and distributor |
Oscillators
Power and Power-On Sequence
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Power Consumption
The maximum power consumption of a module mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
Power Input | Typical Current |
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TBD* |
Table : Typical power consumption.
Power Distribution Dependencies
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Power-On Sequence
Power Rails
Bank Voltages
Variants Currently In Production
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English page | German page |
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Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference Document |
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supply voltage... | V | - | ||
Storage temperature | °C | - |
Table : Module absolute maximum ratings.
Recommended Operating Conditions
Parameter | Min | Max | Units | Reference Document |
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supply voltage... | ||||
Operating temperature |
Table : Module recommended operating conditions.
Physical Dimensions
Board size: ...mm × ...mm. Please download the assembly diagram for exact numbers
PCB thickness: ca. ...mm
The board meets the ... Specification...
All dimensions are given in millimeters.
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Revision History
Hardware Revision History
Date | Revision | Notes | PCN | Documentation Link |
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- | 02 | current available board revision | - | TEC0850-02 |
- | 01 | First production release | - | - |
Table 24: Module hardware revision history
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Document Change History
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Table 25: Document change history
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Disclaimer
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