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Template Revision 2.0 - on construction TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM" |
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Important General Note: |
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anchor | Table_1 |
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title | Table 1: Initial delivery state of programmable devices on the module. |
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orientation | portrait |
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widths | 2*,2*,4* | |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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.. | .. | .. | OTP Flash area | Empty | Not programmed. |
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Front panel USB-C Interface connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.
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anchor | Table_x |
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title | Table x: FTDI Signals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FT601Q Signal | FPGA Pin |
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FIFO_CLK |
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See FT600Q-FT601Q
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See FT600Q-FT601Q IC Datasheet for interface details.
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The TEC0850 board has 30 MGT lines routed to backplane connectors.
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Table_x | title | Table x: MGT Banks |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Bank | Connector | Lanes |
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PL 128 | J4G |
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and J4H | 4 | PL 129 | J5A and J5B | 4 | PL 130 | J5C and J5D | 4 | PL 230 | J4G and J4H | 4 | PL 229 | J5A and J5B | 4 | PL 228 | J5C and J5D | 4 | PS 505 | J1A | 4 |
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MGT reference clocks are connected to banks 129, 229 and 505. Banks 128 and 130 should share clock from bank 129, banks 230 and 228 from bank 229.
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Main IO interfaces are shown on the image below.
PS MIO Configuration
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anchor | Table_x |
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title | Table x: Default MIO Configuration |
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sortEnabled | false |
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MIO | Interface |
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MIO 0...12 | QSPI Flash Memory | MIO 20...21 | I2C 1 | MIO 22...23 | UART 0 | MIO 26...37 | GEM 0 | MIO 46...51 | SD 1 | MIO 52...63 | USB 0 | MIO 64...75 | USB 1 | MIO 76...77 | MDIO 0 |
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Table 10: Default MIO Configuration
MAX10 System Controller
System controller chip is Intel MAX10 10M08SAU169C8G Chip with board control firmware.
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The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.
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Scroll Title |
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anchor | Table_x |
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title | Table x: SI5345 I2C address |
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I2C address | Chip | Description |
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0x69 | U14 Si5345 | Clock generator and distributor |
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Oscillators
FTDIs
FT2232H
FT601Q-B-T
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The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.
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anchor | Table_x |
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title | Table x: EEPROMs I2C Addresses |
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I2C address | Chip | Description |
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0x50 | U63 24AA128T-I/ST | 128K Serial EEPROM | 0x53 | U64 24AA025E48T-I/OT | 2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity |
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USB PHY
Gigabit Ethernet PHY
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Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate.
DIP-Switches
S1
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Table_x | title | Table x: LEDs |
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sortEnabled | false |
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cellHighlighting | true |
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Switch | Description |
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1 | Boot Mode 0 | 2 | Boot Mode 1 | 3 | Boot Mode 2 | 4 | Boot Mode 3 |
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See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description. Most common modes are
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Scroll Title |
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anchor | Table_x |
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title | Table x: Recommended Boot Modes |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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2 | SW1:1 |
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JTAG Boot Mode | ON | ON | ON | ON | Quad-SPI | ON | ON | ON | OFF | SD Card | ON | ON | OFF | OFF |
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S2
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Table_x | title | Table x: S2 DIP Switch |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Switch | Description |
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1 | SC JTAGEN | 2 | EEPROM WP (Write protect) | 3 | FPGA PUDC | 4 | SC Switch (Reserved for |
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Buttons
LEDs
Scroll Title |
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anchor | Table_x |
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title | Table x: LEDs |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Buttons
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LED | Signal | Chip | Pin | Description |
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Front panel LED 1 (Red) | LED_FP_1 | FPGA U1 | AF15 | PL User defined LED | Front panel LED 2 (Green) | LED_FP_2 | FPGA U1 | AG15 | PL User defined LED | Front panel LED 3 (Green) | LED_FP_3 | FPGA U1 | AE15 | PL User defined LED | Front panel LED 4 (Green) | LED_FP_4 | SC U18 | M4 | Power Good |
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Power and Power-On Sequence
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Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.Electronic Wiki FAQ.
Scroll Title |
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anchor | Table_x |
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title | Table x: Typical power consumption. |
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orientation | portrait |
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sortEnabled | false |
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cellHighlighting | true |
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Power Input | Typical Current |
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| TBD* |
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Table : Typical power consumption.
Power Distribution Dependencies
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Voltage Monitor Circuit
Power Rails
Bank Voltages
Technical Specifications
Absolute Maximum Ratings
Voltages
Technical Specifications
Absolute Maximum Ratings
Scroll Title |
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anchor | Table_x |
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title | Table x: Module absolute maximum ratings. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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anchor | Table_x |
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title | Table x: Module absolute maximum ratings.Parameter | Min | Max | Units | Reference Document |
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Scroll Title |
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anchor | Table_x |
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title | Table x: Module absolute maximum ratings.ratings. |
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orientation | portrait |
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sortDirection | ASC |
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Parameter | Min | Max | Units | Reference Document |
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Scroll Title |
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anchor | Table_x |
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title | Table x: Shop Overview |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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Revision History
Hardware Revision History
Scroll Title |
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anchor | Table_x |
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title | Table x: Module absolute maximum ratings. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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widths | *,*,*,*,100% | |
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sortEnabled | false |
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Date | Revision | Notes | PCN | Documentation Link |
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- | 01 | Prototypes |
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Scroll Title |
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anchor | Table_x |
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title | Table x: Document change history. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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widths | 2*,*,3*,4* | |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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| modified-date |
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| modified-date |
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dateFormat | yyyy-MM-dd |
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infoType | Current version |
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dateFormat | yyyy-MM-dd |
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prefix | v. |
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type | Flat |
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infoType | Modified by |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| | -- | all | Page info |
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infoType | Modified users |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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