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Following block diagram visualizes the connection of the SC FPGA with the Zynq Ultrascale+ MPSoC via 4 PS MIO pins (MIO22 ... 25), PS Config Config control signals and 10 singled ended PL HD bank 48 I/O pins (MAX_IO1 ... MAX_IO10):
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| anchor | Figure_2 |
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| title | Figure 2: TEF1001-02 main components |
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| draw.io Diagram |
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| border | true |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramName | TEC0850 SC TO Zynq connections |
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| simpleViewer | false |
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| width | |
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| diagramWidth | 641 |
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| revision | 2 |
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| Scroll Title |
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| anchor | Table_x |
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| title | Table x: SI5345 I2C address |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FT2232H U3 Pin | Signal Schematic Name | Connected to | Notes |
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| Pin 12, ADBUS0 | TCK | SC FPGA U18 bank 6, pin G9
| JTAG interface | | Pin 13, ADBUS1 | TDI | SC FPGA U18 bank 6, pin F10 | | Pin 14, ADBUS2 | TDO | SC FPGA U18 bank 6, pin E10 | | Pin 15, ADBUS3 | TMS | SC FPGA U18 bank 6, pin D9 | | Pin 32, BDBUS0 | BDBUS0 | SC FPGA U18 bank 6, pin B11 | user configurable | | Pin 33, BDBUS1 | BDBUS1 | SC FPGA U18 bank 6, pin A12 | | Pin 34, BDBUS2 | BDBUS2 | SC FPGA U18 bank 6, pin B12
| | Pin 35, BDBUS3 | BDBUS3 | SC FPGA U18 bank 6, pin C11 | | Pin 37, BDBUS4 | BDBUS4 | SC FPGA U18 bank 6, pin B13 | | Pin 38, BDBUS5 | BDBUS5 | SC FPGA U18 bank 6, pin C12 | | Pin 39, BDBUS6 | BDBUS6 | SC FPGA U18 bank 6, pin C13 | | Pin 40, BDBUS7 | BDBUS7 | SC FPGA U18 bank 6, pin D11 | | Pin 42, BCBUS0 | BCBUS0 | SC FPGA U18 bank 6, pin D12 | | Pin 46, BCBUS1 | BCBUS1 | SC FPGA U18 bank 6, pin E13 | | Pin 47, BCBUS2 | BCBUS2 | SC FPGA U18 bank 6, pin E12 | | Pin 48, BCBUS3 | BCBUS3 | SC FPGA U18 bank 6, pin F13 | | Pin 49, BCBUS4 | BCBUS4 | SC FPGA U18 bank 6, pin F12 |
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FT601Q
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| anchor | Figure_11 |
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| title | Figure 11: CAN interface |
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| Scroll Only |
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Quad-SPI Flash Memory
Board has two N25Q512A11G1240E connected in a dual parallel mode.
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| border | true |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramName | TEC0850 USB3 to FIFO |
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| simpleViewer | false |
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| width | |
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| diagramWidth | 641 |
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| revision | 1 |
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| Scroll Title |
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| anchor | Figure_11 |
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| title | Figure 11: CAN interface |
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EEPROMs
Quad-SPI Flash Memory
On-board QSPI flash memory U24 and U25 on the TEC0850 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
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| anchor | Figure_11 |
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| title | Figure 11: CAN interface |
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| IC | Name | Memory Density | Connected to | Notes |
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| QSPI Flash U24 | N25Q256A11E1240E | 256 Mbit (32 MByte) | QSPI0: MIO0 ... MIO5 | dual parallel booting possible, 64 MByte total QSPI Flash memory connected via Dual QSPI MIO0 ... MIO12 |
| QSPI Flash U25 | N25Q256A11E1240E | 256 Mbit (32 MByte) | QSPI0: MIO7 ... MIO12 |
Quad SPI Flash memory ICs U24 and U25 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.
| MIO | Signal Schematic Name | Flash U24 Pin |
| MIO | Signal Schematic Name | Flash U25 Pin |
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| 0 | MIO0 | B2 |
| 7 | MIO7 | C2 |
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| 1 | MIO1 | D2 |
| 8 | MIO8 | D3 |
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| 2 | MIO2 | C4 |
| 9 | MIO9 | D2 |
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| 3 | MIO3 | D4 |
| 10 | MIO10 | C4 |
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| 4 | MIO4 | D3 |
| 11 | MIO11 | D4 |
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| 5 | MIO5 | C2 |
| 12 | MIO12 | B2 |
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EEPROMs
The TEC0850 board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip, the I²C interfaces is connected to Zynq MPSoC bank 502 MIO 20...21 pins:
The clock generator U14 is programmable via the on-board I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.
| Scroll Title |
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| anchor | Figure_11 |
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| title | Figure 11: CAN interface |
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| Scroll Title |
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| anchor | Table_x |
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| title | Table x: EEPROMs I2C Addresses |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| I2C address | Chip | Description |
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| 0x50 | U63 24AA128T-I/ST | 128K Serial EEPROM | | 0x53 | U64 24AA025E48T-I/OT | 2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity |
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USB PHY
USB2 PHY U15 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator U16.
| Scroll Title |
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| anchor | Figure_11 |
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| title | Figure 11: CAN interface |
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| PHY Pin | Connected to | Notes |
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| ULPI | PS bank MIO52 ... MIO63 | Zynq Ultrascale+ USB0 MIO pins are connected to the PHY |
| REFCLK | - | 52MHz from on board oscillator U16 |
| REFSEL[0..2] | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz) |
| RESETB | SC CPLD U27, bank 4, Pin: M2 | Low active USB2 PHY Reset (pulled-up to PS_1.8V) |
| DP, DM | 4-port USB3 Hub U4 | USB2 data lane |
| CPEN | - | External USB power switch active-high enable signal |
| VBUS | 5V | Connected to USB VBUS via a series of resistors, see schematic |
| ID | - | For an A-device connect to the ground. For a B-device, leave floating |
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U27, bank 4, pin K2.
Board has Marvell Alaska 88E1512 Ethernet PHY which use MDIO address 1.
| Scroll Title |
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| anchor | Figure_11 |
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| title | Figure 11: CAN interface |
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8Bit DACs
Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate.
| Scroll Title |
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| anchor | Figure_11 |
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| title | Figure 11: CAN interface |
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DIP-Switches
S1
| Scroll Title |
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| anchor | Table_x |
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| title | Table x: LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Switch | Description |
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| 1 | Boot Mode 0 | | 2 | Boot Mode 1 | | 3 | Boot Mode 2 | | 4 | Boot Mode 3 |
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See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description. Most common modes areThe clock generator U14 is programmable via the on-board I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.
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| anchor | Table_x |
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| title | Table x: EEPROMs I2C AddressesRecommended Boot Modes |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| I2C address | Chip | Description |
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| 0x50 | U63 24AA128T-I/ST | 128K Serial EEPROM |
| 0x53 | U64 24AA025E48T-I/OT | 2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity |
USB PHY
Gigabit Ethernet PHY
Board has Marvell Alaska 88E1512 Ethernet PHY which use MDIO address 1.
8Bit DACs
Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate.
DIP-Switches
| Boot Mode | SW1:4 | SW1:3 | SW1:2 | SW1:1 |
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| JTAG Boot Mode | ON | ON | ON | ON | | Quad-SPI | ON | ON | ON | OFF | | SD Card | ON | ON | OFF | OFF |
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S2S1
| Scroll Title |
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| anchor | Table_x |
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| title | Table x: LEDsS2 DIP Switch |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Boot Mode 0 | | 2 | Boot Mode 1 | | 3 | Boot Mode 2 | | 4 | Boot Mode 3 | |
See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description. Most common modes are
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| anchor | Table_x |
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| title | Table x: Recommended Boot Modes |
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S2
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| anchor | Table_x |
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| title | Table x: S2 DIP Switch |
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| SC JTAGEN | | 2 | EEPROM WP (Write protect) | | 3 | FPGA PUDC | | 4 | SC Switch (Reserved for future use) |
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| DIP-switch S3 | Signal Schematic Name | Connected to | Functionality | Notes |
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| S3-1 | | Zynq MPSoC U1, pin AD15 | Positions
ON: PUDC_B is Low
OFF: PUDC_B is HIGH | Internal pull-up resistors during configuration
are enabled at ON-position,means I/O's are 3-stated
until configuration of the FPGA completes. |
| S3-2 | | SC CPLD U27, bank 0, pin A16 | Positions
ON: SC CPLD's JTAG enabled
OFF: SC CPLD's JTAG disabled | JTAG interface of the SC CPLD, accessible on
XMOD header J35 |
| S3-3 | | SC CPLD U27, bank 0, pin E17 | set 2-bit code for boot mode selection | CPLD Firmware Documentation Section: Boot Mode |
| S3-4 | | SC CPLD U27, bank 0, pin D16 |
| DIP-switch S4 | Signal Schematic Name | Connected to | Functionality | Notes |
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| S4-1 | | SC CPLD U27, bank 0, pin D18 | user defined | For functionalities of these switches in the
current CPLD firmware, refer to the
CPLD Firmware Documentation. |
| S4-2 | | SC CPLD U27, bank 0, pin D16 |
| S4-3 | | SC CPLD U27, bank 0, pin C19 |
| S4-4 | | SC CPLD U27, bank 0, pin C18 |
Buttons
There are two switch buttons available to the user connected to the SC CPLD U27:
| Button | Connected to | Notes |
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| S1 | SC CPLD U27, bank 0, pin F13 | high active logic, connected to 3V3SB, functionality depends on the current firmware of the SC CPLD U27
refer to the documentation |
| S2 | SC CPLD U27, bank 0, pin G13 |
LEDs
The TEC0850 board is equipped with several LEDs to signal current states and activities.
Buttons
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| Scroll Title |
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| anchor | Table_x |
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| title | Table x: LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| LED | Signal | Chip | Color | Connected toPin |
| Description and Notes |
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| Front panel LED 1 (Red) | LED_FP_1 |
| FPGA U1 | AF15 | PL User defined LED | | Front panel LED 2 (Green)LED_FP_2 |
| FPGA U1 | AG15 | PL User defined LED | | Front panel LED 3 (Green) | LED_FP_3 |
| FPGA U1 | AE15 | PL User defined LED | | Front panel LED 4 (Green)LED_FP_4 |
| SC U18 | M4 | Power Good |
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Power and Power-On Sequence
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