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anchor	Figure_2
title	Figure 2: TEF1001-02 main components

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Programmable Clock Generator

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Following table shows on-board Silicon Labs I²C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:

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title	Figure 11: CAN interface

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Channel A of the FTDI IC is configured as JTAG interface (MPSSE) connected to the SC FPGA U18, the JTAG signals are forwarded to the JTAG interface of the Zynq MPSoC on PS config bank 503.

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title	Figure 11: CAN interface

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IC

Name

Memory Density

Connected to

Notes

QSPI Flash U24

N25Q256A11E1240E

256 Mbit (32 MByte)

QSPI0: MIO0 ... MIO5

dual parallel booting possible, 64 MByte total QSPI Flash memory

connected via Dual QSPI MIO0 ... MIO12

QSPI Flash U25

N25Q256A11E1240E

256 Mbit (32 MByte)

QSPI0: MIO7 ... MIO12

Quad SPI Flash memory ICs U24 and U25 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.

MIO	Signal Schematic Name	Flash U24 Pin	MIO	Signal Schematic Name	Flash U25 Pin
0	MIO0	B2	7	MIO7	C2
1	MIO1	D2	8	MIO8	D3
2	MIO2	C4	9	MIO9	D2
3	MIO3	D4	10	MIO10	C4
4	MIO4	D3	11	MIO11	D4
5	MIO5	C2	12	MIO12	B2

EEPROMs

The TEC0850 board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip, the I²C interfaces is connected to Zynq MPSoC bank 502 MIO 20...21 pins:

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title	Table x: EEPROMs I2C Addresses

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PHY Pin	Connected to	Notes
ULPI	PS bank MIO52 ... MIO63	Zynq Ultrascale+ USB0 MIO pins are connected to the PHY
REFCLK	-	52MHz from on board oscillator U16
REFSEL[0..2]	-	All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETB	SC CPLD U27, bank 4, Pin: M2	Low active USB2 PHY Reset (pulled-up to PS_1.8V)
DP, DM	4-port USB3 Hub U4	USB2 data lane
CPEN	-	External USB power switch active-high enable signal
VBUS	5V	Connected to USB VBUS via a series of resistors, see schematic
ID	-	For an A-device connect to the ground. For a B-device, leave floating

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512, which use MDIO address 1.. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U27, bank 4, pin K2.

Board has Marvell Alaska 88E1512 Ethernet PHY which use MDIO address 1.

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8Bit DACs

Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate.

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Switch	Description
1	SC JTAGEN
2	EEPROM WP (Write protect)
3	FPGA PUDC
4	SC Switch (Reserved for future use)

DIP-switch S3	Signal Schematic Name	Connected to	Functionality	Notes
S3-1	PUDC_B	Zynq MPSoC U1, pin AD15	Positions ON: PUDC_B is Low OFF: PUDC_B is HIGH	Internal pull-up resistors during configuration are enabled at ON-position,means I/O's are 3-stated until configuration of the FPGA completes.
S3-2	JTAGENB	SC CPLD U27, bank 0, pin A16	Positions ON: SC CPLD's JTAG enabled OFF: SC CPLD's JTAG disabled	JTAG interface of the SC CPLD, accessible on XMOD header J35
S3-3	SC_SW1	SC CPLD U27, bank 0, pin E17	set 2-bit code for boot mode selection	CPLD Firmware Documentation Section: Boot Mode
S3-4	SC_SW2	SC CPLD U27, bank 0, pin D16	set 2-bit code for boot mode selection	CPLD Firmware Documentation Section: Boot Mode
DIP-switch S4	Signal Schematic Name	Connected to	Functionality	Notes
S4-1	U_SW1	SC CPLD U27, bank 0, pin D18	user defined	For functionalities of these switches in the current CPLD firmware, refer to the CPLD Firmware Documentation.
S4-2	U_SW2	SC CPLD U27, bank 0, pin D16
S4-3	U_SW3	SC CPLD U27, bank 0, pin C19
S4-4	U_SW4	SC CPLD U27, bank 0, pin C18

Buttons

There are two switch buttons available to the user connected to the SC CPLD U27:

Button

Connected to

Notes

S1

SC CPLD U27, bank 0, pin F13

high active logic, connected to 3V3SB,

functionality depends on the current firmware of the SC CPLD U27
refer to the documentation

S2

SC CPLD U27, bank 0, pin G13

LEDs

The TEC0850 board is equipped with several LEDs to signal current states and activities.

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Trenz Electronic Documentation

Versions Compared

Old Version 60

New Version 61

Key

Programmable Clock Generator

EEPROMs

Gigabit Ethernet PHY

8Bit DACs

Buttons

LEDs