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| Scroll Title |
|---|
| anchor | Table_x |
|---|
| title | Table x: EEPROMs I2C Addresses |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| PHY Pin | Connected to | Notes |
|---|
| ULPI | PS bank MIO52 ... MIO63 | Zynq Ultrascale+ USB0 MIO pins are connected to the PHY | | REFCLK | - | 52MHz from on board oscillator U16 | | REFSEL[0..2] | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz) | | RESETB | SC CPLD U27, bank 4, Pin: M2 | Low active USB2 PHY Reset (pulled-up to PS_1.8V) | | DP, DM | 4-port USB3 Hub U4 | USB2 data lane | | CPEN | - | External USB power switch active-high enable signal | | VBUS | 5V | Connected to USB VBUS via a series of resistors, see schematic | | ID | - | For an A-device connect to the ground. For a B-device, leave floating |
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Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512, which use MDIO address 1.. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21.
| Scroll Title |
|---|
| anchor | Figure_11 |
|---|
| title | Figure 11: CAN interface |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | truefalse |
|---|
| viewerToolbar | true |
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| |
|---|
| fitWindow | false |
|---|
| diagramDisplayName | |
|---|
| lbox | true |
|---|
| revision | 1 |
|---|
| diagramName | TEC0850 GbE PHY |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| diagramWidth | 641 | revision | 1 |
|---|
|
|
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8Bit DACs
Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate.
| Scroll Title |
|---|
| anchor | Figure_11 |
|---|
| title | Figure 11: CAN interface |
|---|
|
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DIP-Switches
There are two 4-bit DIP-witches S3 and S4 present on the TEB0911 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
Table below describes the functionalities of the switches of DIP-switches S3 and S4 at their each positions:
S1
| Scroll Title |
|---|
| anchor | Table_x |
|---|
| title | Table x: LEDs |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Switch | Description |
|---|
| 1 | Boot Mode 0 | | 2 | Boot Mode 1 | | 3 | Boot Mode 2 | | 4 | Boot Mode 3 |
|
...
| Scroll Title |
|---|
| anchor | Table_x |
|---|
| title | Table x: S2 DIP Switch |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Switch | Description |
|---|
| 1 | SC JTAGEN | | 2 | EEPROM WP (Write protect) | | 3 | FPGA PUDC | | 4 | SC Switch (Reserved for future use) |
|
| DIP-switch S3S2 | Signal Schematic Name | Connected to | Functionality | Notes |
|---|
| S3S2-1 | PUDC_B JTAGEN | Zynq MPSoC U1, pin AD15 | Positions
ON: PUDC_B is Low
OFF: PUDC_B is HIGH | Internal pull-up resistors during configuration
are enabled at ON-position,means I/O's are 3-stated
until configuration of the FPGA completes. |
| S3S2-2 | JTAGENB WP | SC CPLD U27, bank 0, pin A16 | Positions
ON: SC CPLD's JTAG enabled
OFF: SC CPLD's JTAG disabled | JTAG interface of the SC CPLD, accessible on
XMOD header J35 |
| S3S2-3 | SC PUDC_ SW1B | SC CPLD U27, bank 0, pin E17 | set 2-bit code for boot mode selectionS | CPLD Firmware Documentation Section: Boot Mode |
| S3S2-4 | SC_SW2 SW4 | SC CPLD U27, bank 0, pin D16 |
|
| DIP-switch S4 | Signal Schematic Name | Connected to | Functionality | Notes |
|---|
| S4-1 | | SC CPLD U27, bank 0, pin D18 | user defined | For functionalities of these switches in the
current CPLD firmware, refer to the
CPLD Firmware Documentation. |
| S4-2 | | SC CPLD U27, bank 0, pin D16 |
| S4-3 | | SC CPLD U27, bank 0, pin C19 |
| S4-4 | | SC CPLD U27, bank 0, pin C18 |
Buttons
There are two is one switch buttons button available to the user connected to the SC CPLD U27:FPGA U18:
| Scroll Title |
|---|
| anchor | Table_x |
|---|
| title | Table x: LEDs |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
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LEDs
The TEC0850 board is equipped with several LEDs to signal current states and activities.
| Scroll Title |
|---|
| anchor | Table_x |
|---|
| title | Table x: LEDs |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| LED | Color | Connected to | Description and Notes |
|---|
| Front panel LED 1 (D1 | Red | ) | Zynq MPSoC PL bank 11, pin | FPGA U1 | AF15 | PL User defined LED | | Front panel LED 2 (D2 | Green | ) | Zynq MPSoC PL bank 11, pin | FPGA U1 | AG15 | PL User defined LED | | Front panel LED 3 (D3 | Green) | FPGA U1 | | Zynq MPSoC PL bank 11, pin AE15 | PL User defined LED | | Front panel LED 4 (D4 | Green) | SC FPGA U18 bank 3, pin M4 | Power Good |
|
Power and Power-On Sequence
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