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Si5345A U14 Pin	Signal Schematic Name	Connected to	Clock Direction	Note
IN0	IN0_P	40.000 MHz Oscillator U75	Input	external reference clock input
IN0	IN0_N	GND	Input	external reference clock input
IN1	-	not connected	Input	not used
IN1	-	not connected	Input	not used
IN2	-	not connected	Input	not used
IN2	-	not connected	Input	not used
IN3	-	not connected	Input	not used
IN3	-	not connected	Input	not used
OUT0	CLK0_P	Quad clock buffer Si53340 U16	Output	reference clock input to Quad clock buffer
OUT0	CLK0_N	Quad clock buffer Si53340 U16	Output	reference clock input to Quad clock buffer
OUT1	PE1_CLK_N	cPCI J5, pin B5	Output	reference clock output to cPCI connector J5
OUT1	PE1_CLK_P	cPCI J5, pin A5	Output
OUT2	PE5_CLK_N	cPCI J5, pin C6	Output
OUT2	PE5_CLK_P	cPCI J5, pin B6	Output
OUT3	PE2_CLK_N	cPCI J5, pin E5	Output
OUT3	PE2_CLK_P	cPCI J5, pin D5	Output
OUT4	PE3_CLK_N	cPCI J5, pin H5	Output
OUT4	PE3_CLK_P	cPCI J5, pin G5	Output
OUT5	PE4_CLK_N	cPCI J5, pin K5	Output
OUT5	PE4_CLK_P	cPCI J5, pin J5	Output
OUT6	PE6_CLK_N	cPCI J5, pin F6	Output
OUT6	PE6_CLK_P	cPCI J5, pin E6	Output
OUT7	PE8_CLK_N	cPCI J5, pin L6	Output
OUT7	PE8_CLK_P	cPCI J5, pin K6	Output
OUT8	PE7_CLK_N	cPCI J5, pin I6	Output
OUT8	PE7_CLK_P	cPCI J5, pin H6	Output
OUT9	CLK9_P	Clock Driver LTC6975 U73	Output	reference clock input to dual clock driver
OUT9	CLK9_N	Clock Driver LTC6975 U73	Output	reference clock input to dual clock driver
XA/XB	XAXB_P	54.000 MHz quartz oscillator Y3	Input	Differential quartz oscillator clock input
XA/XB	XAXB_N	54.000 MHz quartz oscillator Y3	Input	Differential quartz oscillator clock input
SCLK, SDA/SDIO	I2C_SCL I2C_SDA	MIO20 MIO21	BiDir	I²C address 0x69

The clock outputs OUT1 and OUT9 are distributed via clock buffer U16 and clock driver U14 to several PL and MGT banks:

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Si53340 U16 Pin	Signal Schematic Name	Connected to	Clock Direction	Note
Q0	CLK1_P CLK1_N	U1, pin G8 U1, pin G7	Output	GTH bank 229 reference clock input
Q1	CLK2_P CLK2_N	U1, pin Y8 U1, pin Y7	Output	PL HP bank 66 reference clock input
Q2	CLK3_P CLK3_N	U1, pin U27 U1, pin U28	Output	PS GTR Bank 505 reference clock input
Q3	CLK4_P CLK4_N	U1, pin L27 U1, pin L28	Output	GTH bank 129 reference clock input
LTC6957 U14 Pin
OUT1	CK_PLL_P CK_PLL_N	U1, pin AG5 U1, pin AG4	Output	PL HP bank 65 reference clock input
OUT2	CK_P CK_N	Signal 'SATA_SL' Signal 'SATA_SCL'	Output	reference clock input cPCI connector J1, header J13 and SC FPGA U18

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The TEC0850 board is equipped with 2 FTDI chips FT2232H (U4) and FT601Q (U9). Both chips are USB to Multipurpose UART/FIFO bridges which converts signals from USB2 or USB3 to a variety of standard serial and parallel interfaces.

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FT2232H

The TEC0850 board is equipped with the FTDI FT2232H USB2 to JTAG/UART adapter controller connected to micro-USB2 connector J9 to provide JTAG and UART access to the Xilinx Zynq XC7Z010 SoC. There is also a 256-byte configuration EEPROM U6 wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.

Warning

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

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Channel A of the FTDI IC is configured as JTAG interface (Channel A of the FTDI IC is configured as JTAG interface (MPSSE) connected to the SC FPGA U18, the JTAG signals are forwarded to the JTAG interface of the Zynq MPSoC on PS config bank 503.

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FT2232H U3 Pin	Signal Schematic Name	Connected to	Notes
Pin 12, ADBUS0	TCKADBUS0	SC FPGA U18 bank 6, pin G9	JTAG interface
Pin 13, ADBUS1	TDIADBUS1	SC FPGA U18 bank 6, pin F10
Pin 14, ADBUS2	TDOADBUS2	SC FPGA U18 bank 6, pin E10
Pin 15, ADBUS3	TMSADBUS3	SC FPGA U18 bank 6, pin D9
Pin 32, BDBUS0	BDBUS0	SC FPGA U18 bank 6, pin B11	UART and user configurable GPIO's
Pin 33, BDBUS1	BDBUS1	SC FPGA U18 bank 6, pin A12
Pin 34, BDBUS2	BDBUS2	SC FPGA U18 bank 6, pin B12
Pin 35, BDBUS3	BDBUS3	SC FPGA U18 bank 6, pin C11
Pin 37, BDBUS4	BDBUS4	SC FPGA U18 bank 6, pin B13
Pin 38, BDBUS5	BDBUS5	SC FPGA U18 bank 6, pin C12
Pin 39, BDBUS6	BDBUS6	SC FPGA U18 bank 6, pin C13
Pin 40, BDBUS7	BDBUS7	SC FPGA U18 bank 6, pin D11
Pin 42, BCBUS0	BCBUS0	SC FPGA U18 bank 6, pin D12
Pin 46, BCBUS1	BCBUS1	SC FPGA U18 bank 6, pin E13
Pin 47, BCBUS2	BCBUS2	SC FPGA U18 bank 6, pin E12
Pin 48, BCBUS3	BCBUS3	SC FPGA U18 bank 6, pin F13
Pin 49, BCBUS4	BCBUS4	SC FPGA U18 bank 6, pin F12

FT601Q

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Quad-SPI Flash Memory

On-board QSPI flash memory U24 and U25 on the TEC0850 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

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dual parallel booting possible, 64 MByte total QSPI Flash memory

connected via Dual QSPI MIO0 ... MIO12

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The TEC0850 board is equipped with the FTDI FT601Q USB3 to 32bit-FIFO adapter controller connected to USB-C connector J10 to provide access to the Zynq MPSoC PL HP I/O's of bank 64. Also 12 control signals of the FTDI FT601Q are connected to the HP bank 64.

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FT601Q U9 Pin	Signal Schematic Name	Connected to	Notes
Pin 12, ADBUS0	DATA	SC FPGA U18 bank 6, pin G9	user configurable
Pin 13, ADBUS1	DATA	SC FPGA U18 bank 6, pin F10
Pin 14, ADBUS2	DATA	SC FPGA U18 bank 6, pin E10
Pin 15, ADBUS3	DATA	SC FPGA U18 bank 6, pin D9
Pin 32, BDBUS0	DATA	SC FPGA U18 bank 6, pin B11
Pin 33, BDBUS1	DATA	SC FPGA U18 bank 6, pin A12
Pin 34, BDBUS2	DATA	SC FPGA U18 bank 6, pin B12
Pin 35, BDBUS3	DATA	SC FPGA U18 bank 6, pin C11
Pin 37, BDBUS4	DATA	SC FPGA U18 bank 6, pin B13
Pin 38, BDBUS5	DATADATA	SC FPGA U18 bank 6, pin C12
Pin 39, BDBUS6	BDBUS6	SC FPGA U18 bank 6, pin C13
Pin 40, BDBUS7	BDBDATAUS7	SC FPGA U18 bank 6, pin D11
Pin 42, BCBUS0	BCBUS0	SC FPGA U18 bank 6, pin D12
Pin 46, BCBUS1	BCBUS1	SC FPGA U18 bank 6, pin E13
Pin 47, BCBUS2	BCBUS2	SC FPGA U18 bank 6, pin E12
Pin 48, BCBUS3	BCBUS3	SC FPGA U18 bank 6, pin F13
Pin 49, BCBUS4	BCBUS4	SC FPGA U18 bank 6, pin F12

Quad-SPI Flash Memory

On-board QSPI flash memory U24 and U25 on the TEC0850 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each, 64 MByte total QSPI Flash memory. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC, enabling dual parallel booting from QSPI Flash memory. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

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IC	Memory Density	MIO	Signal Schematic Name	Flash Memory Pin
QSPI Flash U24, N25Q256A11E1240E	256 Mbit (32 MByte)	0	MIO0	B2
		1	MIO1	D2
		2	MIO2	C4
		3	MIO3	D4
		4	MIO4	D3
		5	MIO5	C2
QSPI Flash U25, N25Q256A11E1240	256 Mbit (32 MByte)	7	MIO7	C2
		8	MIO8	D3
		9	MIO9	D2
		10	MIO10	C4
		11	MIO11	D4
		12	MIO12	B2

EEPROMs

The TEC0850 board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip, the I²C interfaces is connected to Zynq MPSoC bank 502 MIO 20...21 pins:

Quad SPI Flash memory ICs U24 and U25 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.

...

MIO0

...

MIO7

...

MIO1

...

MIO8

...

MIO2

...

MIO9

...

MIO3

...

MIO10

...

MIO4

...

MIO11

...

MIO5

...

MIO12

...

EEPROMs

The TEC0850 board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip, the I²C interfaces is connected to Zynq MPSoC bank 502 MIO 20...21 pins:

The clock generator U14 is programmable via the on-board I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.

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USB PHY

USB2 PHY U15 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator U16.

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: CAN interface

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The EEPROMs U63 and U64 are programmable via the on-board I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.

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PHY Pin

Connected to

Notes

ULPI

PS bank MIO52 ... MIO63

Zynq Ultrascale+ USB0 MIO pins are connected to the PHY

REFCLK

-

52MHz from on board oscillator U16

REFSEL[0..2]

-

All pins set to GND selects the external reference clock frequency (52.000000 MHz)

RESETB

SC CPLD U27, bank 4, Pin: M2

Low active USB2 PHY Reset (pulled-up to PS_1.8V)

DP, DM

4-port USB3 Hub U4

USB2 data lane

CPEN

-

External USB power switch active-high enable signal

VBUS

5V

Connected to USB VBUS via a series of resistors, see schematic

ID

-

For an A-device connect to the ground. For a B-device, leave floating

Gigabit Ethernet PHY


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I2C address	Chip	Description
0x50	U63 24AA128T-I/ST	128K Serial EEPROM
0x53	U64 24AA025E48T-I/OT	2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity

USB PHY

USB2 PHY U15 is provided by USB3320 from Microchip. The ULPI On-board Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512, which use MDIO address 1.. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3USB0. I/O voltage is fixed at 1.8V for HSTL signaling. The and PHY reference clock input of the PHY is supplied from the on-board 2552.000000 MHz oscillator U21U12.

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8Bit DACs

Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate.

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PHY Pin	Connected to	Notes
ULPI	PS bank MIO52 ... MIO63	Zynq Ultrascale+ USB0 MIO pins are connected to the PHY
REFCLK	-	52MHz from on board oscillator U12
REFSEL[0..2]	-	All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETB	Zynq MPSoC MIO16, pin AM16	Low active USB2 PHY Reset
DP, DM	cPCI connector J1	USB2 data lane
CPEN	-	External USB power switch active-high enable signal
VBUS	5V	Connected to USB VBUS via a series of resistors, see schematic
ID	3.3V	B-device

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512, which use MDIO address 1.. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21.

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DIP-Switches

There are two 4-bit DIP-witches S3 and S4 present on the TEB0911 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

Table below describes the functionalities of the switches of DIP-switches S3 and S4 at their each positions:

S1

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SwitchDescription1Boot Mode 02Boot Mode 13Boot Mode 24Boot Mode 3

See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description. Most common modes are

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8Bit DACs

Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate.

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DIP-Switches

There are two 4-bit DIP-witches S3 and S4 present on the TEC0850 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

Table below describes the functionalities of the switches of DIP-switches S1 and S2 at their each positions:S2

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Switch

Description

1

SC JTAGEN

2

EEPROM WP (Write protect)

3

FPGA PUDC

4

SC Switch (Reserved for future use)

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JTAGEN

DIP-switch S1	Signal Schematic Name	Connected to	Functionality	Notes
S1-1	JTAGEN	SC FPGA U18, bank 1B, pin E5	Positions: OFF: SC FPGA's JTAG enabled ON: SC FPGA's JTAG disabled	switch the JTAG pins to user GPIO's if JTAG is disabled
S1-2	WP	EEPROM U63, pin 7	Positions: OFF: Write Protect is enabled ON: Write Protect is disabled	-
S1-3	PUDC_B	Zynq MPSOC PS Config Bank 503

...

, pin AD15

Positions:
ON: PUDC_B is Low
OFF: PUDC_B is HIGH

Internal pull-up resistors during configuration
are enabled at ON-position

...

WP

...

Positions
ON: SC CPLD's JTAG enabled
OFF: SC CPLD's JTAG disabled

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PUDC_B

...

CPLD Firmware Documentation

Section: Boot Mode

,means I/O's are 3-stated
until configuration of the FPGA completes.

S1

...

-4

SW4

SC

...

FPGA U18, bank

...

8, pin

...

DIP-switch
A5	SC Switch (Reserved for future use)	low active logic

...

S2	Signal Schematic Name	Connected to	Functionality	Notes

...

S2-1

...

U_SW1

...

U_SW2

...

U_SW3

...

MODE3	Zynq MPSOC PS Config Bank 503, pin AD15	set 4-bit code for boot mode selection	See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description Set DIP-switches as bit pattern "S1-4 \| S1-3 \| S1-2 \| S1-1: Boot Mode": ON \| ON \| ON \| ON \|: JTAG Boot Mode ON \| ON \| ON \| OFF \|: Quad-SPI ON \| ON \| OFF \| OFF \|: SD Card
S2-2	MODE2			Zynq MPSOC PS Config Bank 503, pin AD15
S2-3	MODE1			Zynq MPSOC PS Config Bank 503, pin AD15
S2-4	MODE0			Zynq MPSOC PS Config Bank 503, pin AD15

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U_SW4

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Buttons

There is one switch button available to the user connected to the SC FPGA U18:

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Button

Connected to

Notes

S3

SC FPGA U18, bank 5, pin J10

low active logic

Refer documentation of the firmware of SC FPGA U18.

LEDs

The TEC0850 board is equipped with several LEDs to signal current states and activities.

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Trenz Electronic Documentation

Versions Compared

Old Version 62

New Version 63

Key

Quad-SPI Flash Memory

Quad-SPI Flash Memory

EEPROMs

EEPROMs

USB PHY

Gigabit Ethernet PHY

USB PHY

8Bit DACs

Gigabit Ethernet PHY

DIP-Switches

8Bit DACs

DIP-Switches

Buttons

LEDs