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| Scroll Title |
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| anchor | Table_1 |
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| title | Table 1: Initial delivery state of programmable devices on the module. |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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| User configuration EEPROMs (1x Microchip 24AA128T-I/ST, 1x Microchip 24AA025E48T-I/OT) | Empty | Not programmed | | USB2 to FIFO bridge configuration EEPROM (ST M93C66) | Empty | Not programmed | | Si5345A programmable PLL NVM OTP | Empty | Not programmed | | 2x QSPI Flash memory | Empty | Not programmed |
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| Page properties |
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- Overview of Boot Mode, Reset, Enables,
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To get started with TEC0850 board, some initial signals should be set decribed in the following table:
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| anchor | Table_2 |
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| title | Table 2: TEC0850 Control Signals |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Control signal | Schematic Names | Connected to | Functionality | Notes |
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| SC JTAGEN |
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| OFF: MAX 10, ON: SoC |
| | EEPROM WP |
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| Write protect, OFF active |
| | FPGA PUDC |
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| ON: internal pull-up resistors enabled, OFF: floating |
| | SC Switch |
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| Reserved for future use | | 4bit boot mode setting code |
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| | Push button S3 |
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| | SC FPGA U18 MAX10 Reset line |
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Signals, Interfaces and Pins
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CompactPCI Connector J1
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| anchor | Table_23 |
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| title | Table 23: cPCI J1 interfaces |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
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| I/O | 1 | - | SC FPGA U18 Bank 6 | +3V_D | control signals in cPCI pin assingment | | 6 | - | SC FPGA U18 Bank 8 | +3V_D | control signals in cPCI pin assingment | | I²C | 2 | - | SC FPGA U18 Bank 1A | +3V_D | SC FPGA U18 I²C interface | | JTAG | 4 | - | SC FPGA U18 Bank 1A | +3V_D | SC FPGA U18 JTAG interface | | MGT | - | 8 (4 x RX/TX) | Bank 502 PS GTR | - | 4x PS GTR lanes | | USB2 | - | 1 (RX/TX) | USB2 PHY U11 | - | USB2 OTG A-Device (host) | | Clock Input | - | 1 | Clock Driver U73 | - | 1x Reference clock input from PLL clock U14 |
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| Scroll Title |
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| anchor | Table_34 |
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| title | Table 34: cPCI J1 MGT lanes |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MGT Lane | Bank | Type | Signal Schematic Name | cPCI Connector Pin | FPGA Pin |
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| 0 | 505 | GTR | - PE1_RX0_P
- PE1_RX0_N
- PE1_TX0_P
- PE1_TX0_N
| J1-D5
J1-E5
J1-A5
J1-B5 | PS_MGTRRXP0_505, AB29
PS_MGTRRXN0_505, AB30
PS_MGTRTXP0_505, AB33
PS_MGTRTXN0_505, AB34 | | 1 | 505 | GTR | - PE1_RX1_P
- PE1_RX1_N
- PE1_TX1_P
- PE1_TX1_N
| J1-J5
J1-K5
J1-G5
J1-H5 | PS_MGTRRXP1_505, Y29
PS_MGTRRXN1_505, Y30
PS_MGTRTXP1_505, AA31
PS_MGTRTXN1_505, AA32 | | 2 | 505 | GTR | - PE1_RX2_P
- PE1_RX2_N
- PE1_TX2_P
- PE1_TX2_N
| J1-E6
J1-F6
J1-B6
J1-C6 | PS_MGTRRXP2_505, W31
PS_MGTRRXN2_505, W32
PS_MGTRTXP2_505, Y33
PS_MGTRTXN2_505, Y34 | | 3 | 505 | GTR | - PE1_RX3_P
- PE1_RX3_N
- PE1_TX3_P
- PE1_TX3_N
| J1-K6
J1-L6
J1-H6
J1-I6 | PS_MGTRRXP3_505, V29
PS_MGTRRXN3_505, V30
PS_MGTRTXP3_505, V33
PS_MGTRTXN3_505, V34 |
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| Scroll Title |
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| anchor | Table_45 |
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| title | Table 45: cPCI J1 clock signals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Clock Signal Schematic Name | cPCI Connector Pin | Header J13 Pin | SC FPGA U18 Pin | Notes |
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| J1-K3
J1-J3 | J13-5
J13-1 | Bank 1B, Pin G1
Bank 1B, Pin G2 | Supplied by 10-output PLL clock U14, cPCI connector J1 clock signal from PLL U14 is
also shared with SC FPGA and header J13 |
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| Scroll Title |
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| anchor | Table_5 |
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| title | Table 5: cPCI J1 VCC/VCCIO |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Available VCC/VCCIO | cPCI Connector Pin | Source | Notes |
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| VIN_12V | J1-A1
J1-D1
J1-E1
J1-G1
J1-H1
J1-J1J1-K1cPCI backplane
| min. cur.: 6.65A |
| Anchor |
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| CompactPCI Connector J4 |
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| CompactPCI Connector J4 |
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Power supply with minimum current capability of 6.65A 5A (60W@12V, CompactPCI spec.) for system startup is recommended.
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| Scroll Title |
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| anchor | Table_31 |
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| title | Table 31: Module absolute maximum ratings |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Parameter | Min | Max | Unit | Reference Document | Notes |
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| VIN_12V | 12 | 14 | V | Intel Enpirion EM2130 data sheet | 12V nominally input voltage, min. current 6.65Avoltage | | VBATT | 2.2 | 5.5 | V | TPS780180300 data sheet | supplied by 3.0V CR1220 battery | | VCCO for HD I/O banks | 1.14 | 3.4 | V | Xilinx document DS925 | - | | VCCO for HP I/O banks | 0.95 | 1.9 | V | Xilinx document DS925 | - | | I/O input voltage for HD I/O banks | -0.2 | VCCO + 0.2 | V | Xilinx document DS925 | - | | I/O input voltage for HP I/O banks | -0.2 | VCCO + 0.2 | V | Xilinx document DS925 | - | | PS I/O input voltage (MIO pins) | -0.2 | VCCO_PSIO + 0.2 | V | Xilinx document DS925 | VCCO_PSIO 1.8V nominally | | SC FPGA U18 I/O input voltage | 0 | VCC | V | Intel MAX 10 data sheet | VCC 3.3V nominally | | Board Operating Temperature Range 1), 2) | 0 | 85 | °C | Xilinx document DS925 | extended grade Zynq MPSoC temperarure range |
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| Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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| Scroll Title |
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| anchor | Table_1 |
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| title | Table 1: Initial delivery state of programmable devices on the module. |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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| User configuration EEPROMs (1x Microchip 24AA128T-I/ST, 1x Microchip 24AA025E48T-I/OT) | Empty | Not programmed | | USB2 to FIFO bridge configuration EEPROM (ST M93C66) | Empty | Not programmed | | Si5345A programmable PLL NVM OTP | Empty | Not programmed | | 2x QSPI Flash memory | Empty | Not programmed |
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