Control signal | Schematic Names | Connected to | Functionality | Notes | SC JTAGEN | OFF: MAX 10, ON: SoC | EEPROM WP | Write protect, OFF active | FPGA PUDC | ON: internal pull-up resistors enabled, OFF: floating | SC Switch | Reserved for future use | Switch / Button | Signal Schematic Names | Connected to | Functionality | Notes |
|---|
| SC JTAGEN | S1-1 | JTAGEN | SC FPGA U18, bank 1B, pin E5 | OFF: MAX 10 JTAG enabled,
ON: Zynq MPSoC JTAG enabled | - |
| EEPROM WP | S1-2 | WP | EEPROM U63, pin 7 | Write protect, active on OFF position | - |
| FPGA PUDC | S1-3 | PUDC_B | Zynq MPSOC PS Config Bank 503, pin AD15 | ON: internal pull-up resistors enabled, OFF: floating | - |
| SC Switch | S1-4 | SW4 | SC FPGA U18, bank 8, pin A5 | low active logic | Reserved for future use |
| 4bit boot mode setting code | S2-1 | MODE3 | Zynq MPSOC PS Config Bank 503, pin R23 | Set 4-bit code for boot mode selection,
most common modes are as follows:
Set DIP-switches as bit pattern
"S1-4 | S1-3 | S1-2 | S1-1 : Boot Mode": ON | ON | ON | ON : JTAG Boot Mode
ON | ON | ON | OFF : Quad-SPI
ON | ON | OFF | OFF : SD Card | See Zynq UltraScale+ Device Technical Reference Manual
page 236 for full boot modes description
|
| S2-2 | MODE2 | Zynq MPSOC PS Config Bank 503, pin T23 |
| S2-3 | MODE1 | Zynq MPSOC PS Config Bank 503, pin R22 |
| S2-4 | MODE0 | Zynq MPSOC PS Config Bank 503, pin T22 |
| Push button | S3 | USR_BTN | SC FPGA U18, bank 5, pin J10 | low active logic | See documentation of the firmware of SC FPGA
U18 for current functionality of the on-board Push Button S3 |
| SC FPGA U18 Reset | header J13, pin 6 | M10_RST | SC FPGA U18, bank 8, pin A7 | low active reset line | - | 4bit boot mode setting code | Push button S3 | SC FPGA U18 MAX10 Reset line |