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The Trenz Electronic TEC0850 board is a CompactPCI card (3U form factor) integrating a Xilinx Zynq UltraScale+ MPSoC, one DDR4 SDRAM SODIMM socket with 64bit wide databusdata bus, max. dual 512 MByte Flash memory for configuration and operation, 24 Gigabit transceivers on PL side and 4 on PS side, powerful switch-mode power supplies for all on-board onboard voltages, USB2 and USB3 FIFO bridges and a large number of configurable I/Os available on the CompactPCI backplane connectors.

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• Zynq UltraScale+ MPSoC ZU15

• Front side interface connectors
  • RJ-45 GbE Ethernet interface
  • Circular push/pull connector with 4x on-board 8bit DAC output
  • MicroSD Card connector
  • USB2 and USB3 USB 2.0 and USB 3.0 to FIFO bridge connector
  • 4x status LEDs
• 4 CompactPCI connectors for backplane connection (3U form factor)
  • 24 GTH lanes
  • 4 PS GTR lanes
  • USB2 USB 2.0 interface
  • 64 Zynq PL HP I/O's
  • 8x PLL clock input
  • JTAG, I²C and 7 user I/O's to MAX10 FPGA

• 64bit DDR4 SODIMM (PS connected), 8 GByte maximum

• Dual parallel QSPI Flash (bootable), 512 MByte maximum

• 26-pin header with 20 Zynq PL HD I/O's
• 3-pin header with 2 MAX10 FPGA I/O's
• System Controller (Altera MAX10 FPGA SoC)
  • Power Sequencing
  • System management and control for MPSoC and on-board onboard peripherals
• Si5345 programmable 10 output PLL clock generator
• Si53340 Quad clock buffer
• 2x 4bit DIP switches
• 1x user push button
• Zynq MPSoC cooling FAN connector
• On-board high-efficiency DC-DC converters

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1. GbE RJ-45 MagJack, J7
2. 5-pin circular push/pull receptacle connector for DAC output, J15
3. Micro USB2 USB 2.0 B receptacle connector, J9
4. MicroSD Card socket, J11
5. USB 3.0 Type C connector, J10
6. LED light pipes J14 integrating LEDs D1 ... D4
7. 4bit DIP-switch, S2
8. 4bit DIP-switch, S1
9. FTDI FT2232 USB2 to FIFO USB 2.0 to UART/JTAG bridge, U4
10. 3-pin PicoBlade header, J8
11. MAX10 FPGA JTAG/UART 10-pin header, J13
12. Altera MAX10 System Controller FPGA, U18
13. 4-Wire PWM fan connector, J17
14. 26-pin IDC header for FPGA PL I/O's, J16
15. DDR4 SO-DIMM 260-pin socket, U3
16. Battery Holder CR1220, B1
17. 256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U24
18. 256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U25
19. DC-DC Converter LT8471IFE @+5VA/-5VA, U74
20. DC-DC Converter EM2130L02QI @VCCINT_0V85, U17
21. DC-DC Converter 171050601 @5V, U50
22. Xilinx Zynq Ultrascale+ MPSoC, U1
23. Si5345A 10-output I²C programmable PLL clock, U14
24. Main power fuse @2.5A/16V, F1
25. cPCI connector, J1
26. cPCI connector, J4
27. cPCI connector, J5
28. cPCI connector, J6
29. FTDI FT601Q USB3 USB 3.0 to FIFO bridge, U9
30. TI THS5641 8bit DAC ,U28
31. TI THS5641 8bit DAC ,U31
32. TI THS5641 8bit DAC ,U29
33. TI THS5641 8bit DAC ,U33
34. Marvell Alaska 88E1512 GbE PHY ,U20
    

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To get started with TEC0850 board, some initial signals should be set decribed described in the following table:

Signals, Interfaces, and Pins

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The TEC0850 board is equipped with 3 CompactPCI high-speed backplane connectors which provides provide serial high-speed interconnects with transmission rates up to 12 Gb/s to the Zynq MPSoCs MGT lanes, high-speed USB2 USB 2.0 interface, and single-ended FPGA I/O pins Zynq MPSoC and the System Controller FPGA.

The connectors support single-ended and differential signaling as the Zynq MPSoC FPGA I/O's are routed from the FPGA banks as LVDS-pairs to the backplane connector.

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The USB3 USB 3.0 to FIFO bridge FTDI FT601Q U9 is connected to the Zynq MPSoC's PL bank 64 and is accessible through USB-C connector J10:

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The SD Card interface of the TEC0850 board is not directly wired to the connector J11 pins , but through a Texas Instruments TXS02612 SD IO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and MIO-bank of the Xilinx Zynq MPSoC. The Micro SD Card has 3.3V signal voltage level, but the PS MIO-bank on the Xilinx Zynq MPSoC has VCCIO of 1.8V.

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RJ45 - Ethernet

On-board Onboard Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 501. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the GbE PHY U20 status LED output.

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DDR4 SODIMM Socket

On the TEC0850 board, there is a DDR4 memory interface U3 with a 64-bit databus data bus width available for SO-DIMM modules connected to the Zynq UltraScale+ DDRC hard memory controller.

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Following table gives an overview about of the memory interface I/O signals of the DDR4 SDRAM SO-DIMM Socket U3:

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On the TEC0850 there is a 10-pin SMT header (2x5, 2.54mm grid size) J13 present which provides access to the JTAG and UART interface of Altera MAX10 System Controller FPGA. The header J13 has a compatible pin assignment to the TEI0004 JTAG programmer for Altera FPGAs, the voltage levels 3.3V is on the header available as a reference I/O-voltage for JTAG and UART.

The 4 JTAG pins of the header J13 are also connected to the cPCI connector J1 and can be used es as user GPIO's of the SC FPGA U18 with othr other functionalities then JTAG.

On the header J13, there is also a reference clock signal from PLL clcok clock U14 available, which can be also used for the SC FPGA U18 and on the cPCI connector J1.

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There is a CR1220 battery holder available to the supply the voltage for the  for  for the Zynq MPSoC's Battery Power Domain (BBRAM and RTC). The battery voltage VBATT should be in the range of 2.2V to 5.5V, use the 3.0V CR1220 battery.

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Onboard Peripherals

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The PS MIO pins are routed to the on-board onboard peripherals as follows:

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The TEC0850 board is equipped with one System Controller FPGA (Intel MAX10 10M08SAU169C8G) with the schematic designators U18. The  SC FPGA is the central system management unit where essential control signals are logically linked by the implemented logic in FPGA firmware, which generates output signals to control the system, the on-board onboard peripherals, and the interfaces. Interfaces like JTAG and UART between the FTDI FT2232H chip and to the Zynq MPSoC are by-passed, forwarded and controlled by the System Controller FPGA.

Other tasks of the System Controller FPGA are the monitoring of the power-on sequence and to display the programming state of the FPGA module. The functionalities and configuration of the pins depend depending on the SC FPGA's firmware. The documentation of the firmware of SC FPGA U18 contains detailed information on this matter.

The Sytem System Controller FPGA is connected to the Zynq Ultrascale+ MPSoC through MIO and PL pins. The signals of these pins are forwarded by the SC FPGA to control some of the on board onboard peripherals.

Following block diagram visualizes the connection of the SC FPGA with the Zynq Ultrascale+ MPSoC via 4 PS MIO pins (MIO22 ... 25), PS Config control signals and 10 singled ended PL HD bank 48 I/O pins (MAX_IO1 ... MAX_IO10):

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There is a Si5345A U14, Silicon Labs I²C programmable 10-output PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and on-board onboard peripherals.

Following table shows on-board Silicon onboard Silicon Labs I²C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:

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The clock generator U14 is programmable via the on-board onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.

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The TEC0850 board is equipped several on-board onboard oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board onboard peripherals with reference clock-signals:

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The TEC0850 board is equipped with the FTDI FT2232H USB2 to JTAG/UART adapter controller connected to micro-USB2 connector J9 to provide JTAG and UART access to the Xilinx Zynq XC7Z010 SoC. There is also a 256-byte configuration EEPROM U6 wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI data sheet datasheet to get information about the capacity of the FT2232H chip.

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Channel B can be used as UART Interface routed to SC FPGA U18, 11 I/O's of Channel B are is routed to are usable for example as GPIOs and other standard interfaces.

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The TEC0850 board is equipped with the FTDI FT601Q USB3 to 32bit-FIFO adapter controller connected to USB-C connector J10 to provide access to the Zynq MPSoC PL HP I/O's of bank 64. Also, 13 control signals of the FTDI FT601Q are connected to the HP bank 64.

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On-board QSPI flash memory U24 and U25 on the TEC0850 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each, 64 MByte total QSPI Flash memory. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC, enabling dual parallel booting from QSPI Flash memory. This non volatile nonvolatile memory is used to store an initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

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The TEC0850 board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip, the I²C interfaces is are connected to Zynq MPSoC bank 502 MIO 20...21 pins:

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The EEPROMs U63 and U64 are programmable via the on-board onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.

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Gigabit Ethernet PHY

On-board Onboard Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512, which use MDIO address 1.. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21.

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There are two 4-bit DIP-witches S3 and S4 present on the TEC0850 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

Table The table below describes the functionalities of the switches of DIP-switches S1 and S2 at their each positionsevery position:

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The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide provides a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power supply with a minimum current capability of 5A (60W@12V, CompactPCI spec.) for system startup is recommended.

The TEC0850 board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet an embedded system power management requirement by advanced power management features. This These features allow to offset offsetting the power and heat constraints against overall performance and operational efficiency.

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There are following dependencies how the initial 24V voltage from the main power pins on cPCI slot J1 is distributed to the on-board onboard DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

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The TEC0850 board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board onboard DC-DC converters dedicated to the particular Power Domains and powering up the on-board onboard voltages.

On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller FPGA U18:

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Hence, those three power instances will be powered up consecutively when the Power-Good signals of the previous instance is are asserted.

Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.

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It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning that all on-board onboard voltages have become stable and the module is properly powered up.

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Recommended Operating Conditions

1) Temperature range may vary depending on assembly options

2) The operating temperature range of the Zynq MPSoC, SC FPGA SoC and on-board onboard peripherals are a junction and also ambient operating temperature ranges

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