TRM Name always "TE Series Name" +TRM, for example, "TE0720 TRM"
...
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<type>_<main section>_<name>
type: Figure, Table
main section:
"OV" for Overview
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"OBP" for On board Peripherals,
"PWR" for Power and Power-On Sequence,
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"Figure_PWR_
"Figure_BD" for Block Diagramm
"Figure_MC" for Main Components
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Document
RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>...
Following diagram gives an overview of the CompactPCI backplane connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller FPGA U18:
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Figure_SIP_CompactPCI
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Figure 3: TEC0850-02 CompactPCI I/O and high-speed interfaces
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Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the cPCI connectors:
Supplied by 10-output PLL clock U14, optional if decoupling capacitors and resistors are fitted (see schematic), also shared with SC FPGA and header J13.
...
Anchor
CompactPCI Connector J2
CompactPCI Connector J2
Optional CompactPCI Connector J2
CompactPCI connector J2 is not fittedby default on the TEC0850 board by default, but is necessary if the second optional USB2 PHY U13 if fitted and its USB2 differential serial data interface is connected to the cPCI connector J2.
The USB 3.0 to FIFO bridge FTDI FT601Q U9 is connected to the Zynq MPSoC's PL bank 64 and is accessible through USB-C connector J10:
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Table_SIP_j10_usb-c
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Table 10: USB-C connector J10
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Interface
Signal Schematic Names
Connected to
Notes
USB3 data lane
SSRX_P
SSRX_N
SSTXX_P
SSTXX_N
USB C Connector J10
-
USB2 data lane
SS_D_P
SS_D_N
USB C Connector J10
-
Control Lines
FTDI_RESET_N
WAKEUP_N
SIWU_N
TXE_N
RXF_N
WR_N
RD_N
OE_N
BE_0
BE_1
BE_2
BE_3
FIFO_CLK
PL bank 64
-
Parallel GPIO's
DATA0
.
.
DATA31
PL bank 64
32bit FIFO register
...
The Digilent plug-in software and cable drivers must be installed on your machine for you to be able to use JTAG interface.
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Figure_SIP_jtag_uart
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Figure 5: JTAG/UART Interface
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The USB2 to FIFO bridge FTDI FT2232H U4 is connected to the SC FPGA U18 and is accessible through Micro-USB2 connector J9:
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Table_SIP_micro_usb2
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Table 11: Micro-USB2 connector J9
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Interface
Signal Schematic Names
Connected to
Notes
USB2 data lane
USB_P
USB_N
Micro-USB2 connector J9
-
Control Lines
FTDI_RST
SC FPGA U18, bank 6
-
Parallel GPIO's
ADBUS0
ADBUS1
ADBUS2
ADBUS3
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
SC FPGA U18, bank 6
-
...
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Figure 6: MicroSD Card interface
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Onboard Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 501. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the GbE PHY U20 status LED output.
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Figure_SIP_eth
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Figure 7: Gigabit Ethernet Interface
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Figure_SIP_ddr4
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Figure 8: DDR4 SDRAM SODIMM socket
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Following table gives an overview of the memory interface I/O signals of the DDR4 SDRAM SO-DIMM Socket U3:
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Table_SIP_ddr4
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Table 12: DDR4 SDRAM SO-DIMM socket U3
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DDR4 SDRAM I/O Signal
Signal Schematic Name
Connected to
Notes
Address inputs
DDR4-A0 ... DDR4-A16
PS DDR Bank 504
-
Bank address inputs
DDR4-BA0 / DDR4-BA1
-
Bank group inputs
DDR4-BG0 / DDR4-BG1
-
Differential clocks
DDR4-CLK0_P
DDR4-CLK0_N
DDR4-CLK1_P
DDR4-CLK1_N
2 x DDR4 clock
Data input/output
DQ0 ... DQ63
-
Check bit input/output
CB0 ... CB7
-
Data strobe (differential)
DDR4-DQS0_P
DDR4-DQS0_N
...
DDR4-DQS8_P
DDR4-DQS8_N
-
Data mask and data bus inversion
DDR4-DM0 ... DDR4-DM8
-
Serial address inputs
DDR4-SA0 ... DDR4-SA2
address range configuration on I²C bus
Control Signals
DDR4-CS_N0 / DDR4-CS_N1
chip select signal
DDR4-ODT0 / DDR4-ODT1
On-die termination enable
DDR4-RESET
nRESET
DDR4-PAR
Command and address parity input
DDR4-CKE0 / DDR4-CKE1
Clock Enable
DDR4-ALERT
CRC error flag
DDR4-ACT
Activation command input
DDR4-EVENT
Temperature event
I²C
DDR4-SCL
DDR4-SDA
not connected
-
...
The TI THS4631D digital to analog converter wired to the operational amplifier circuitry creating the DAC unit with a voltage output range from -0.5V ... 0.5V. See TI THS5641 datasheet and schematic how to control the DAC unit and to set the analog output voltages on connector J15.
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Figure_SIP_dac
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Figure 9: 4x 8bit DAC units
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There is a 26-pin IDC header (2x13, 1.27mm grid size) J16 available on the TEC0850 board which exposes the 20 FPGA HD I/O's of PL bank 47 to the user. The PL bank 47 has 3.3V VCCO bank voltage, on the header J16 there also the voltage levels 3.3V and 5V available. The I/O's can be accessed with a corresponding IDC connector.
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Figure_SIP_idc_mpsoc_pl
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Figure 10: Zynq MPSoC PL I/O's IDC pin-header
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Figure 11: 10-pin JTAG/UART header
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Figure 12: 3-pin PicoBlade header
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There is a CR1220 battery holder available to the supply the voltage for the Zynq MPSoC's Battery Power Domain (BBRAM and RTC). The battery voltage VBATT should be in the range of 2.2V to 5.5V, use the 3.0V CR1220 battery.
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Figure 13: Backup-Battery Holder
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Figure 14: 4-wire PWM FAN connector
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The PS MIO pins are routed to the onboard peripherals as follows:
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Table_OBP_default_mio
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Table 13: Default MIO Configuration
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PS MIO
Function
Connected to
0
QSPI*
U24-B2, CLK
1
QSPI*
U24-D2, DO/IO1
2
QSPI*
U24-C4, WP/IO2
3
QSPI*
U24-D4, HOLD/IO3
4
QSPI*
U24-D3, DI/IO0
5
QSPI*
U24-C2, CS
6
-
not connected
7
QSPI*
U25-C2, CS
8
QSPI*
U25-D3, DI/IO0
9
QSPI*
U25-D2, DO/IO1
10
QSPI*
U17-C4, WP/IO2
11
QSPI*
U25-D4, HOLD/IO3
12
QSPI*
U25-B2, CLK
13 ... 15
-
not connected
16
USB2 PHY Reset
USB2 PHY U11, pin27
17
USB2 PHY Reset
USB2 PHY U13, pin27 (optional, PHY not fitted by default)
18 ... 19
-
not connected
20 ...21
PS MIO I²C
I²C peripherals
22 ... 25
user MIO
SC FPGA U18, bank 2
26 ... 38
RGMII
GbE PHY U20
39 ... 44
-
not connected
45 ... 51
SD IO
MicroSD Card socket J11
52 ... 63
USB2 ULPI
USB2 PHY U11
64 ... 75
USB2 ULPI
USB2 PHY U13 (optional, PHY not fitted by default)
76 ... 77
ETH MDC / MDIO
GbE PHY U20
* Flash is used as QSPI dual parallel
...
Following block diagram visualizes the connection of the SC FPGA with the Zynq Ultrascale+ MPSoC via 4 PS MIO pins (MIO22 ... 25), PS Config control signals and 10 singled ended PL HD bank 48 I/O pins (MAX_IO1 ... MAX_IO10):
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Figure_OBP_max10_sc
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Figure 15: TEC0850 MAX10 System Controller FPGA
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There is a Si5345A U14, Silicon Labs I2C programmable 10-output PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and onboard peripherals.
Following table shows onboard Silicon Labs I2C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:
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Table_OBP_si5345
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Table 14: SI5345 Clock Outputs
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Si5345A U14 Pin
Signal Schematic Name
Connected to
Signal Direction
Note
IN0
IN0_P
40.000 MHz Oscillator U75
Input
external reference clock input
IN0_N
GND
IN1
-
not connected
Input
not used
-
not connected
IN2
-
not connected
Input
not used
-
not connected
IN3
-
not connected
Input
not used
-
not connected
OUT0
CLK0_P
Quad clock buffer Si53340 U16
Output
reference clock input to Quad clock buffer
CLK0_N
OUT1
PE1_CLK_N
cPCI J5, pin B5
Output
reference clock output to cPCI connector J5
PE1_CLK_P
cPCI J5, pin A5
OUT2
PE5_CLK_N
cPCI J5, pin C6
Output
PE5_CLK_P
cPCI J5, pin B6
OUT3
PE2_CLK_N
cPCI J5, pin E5
Output
PE2_CLK_P
cPCI J5, pin D5
OUT4
PE3_CLK_N
cPCI J5, pin H5
Output
PE3_CLK_P
cPCI J5, pin G5
OUT5
PE4_CLK_N
cPCI J5, pin K5
Output
PE4_CLK_P
cPCI J5, pin J5
OUT6
PE6_CLK_N
cPCI J5, pin F6
Output
PE6_CLK_P
cPCI J5, pin E6
OUT7
PE8_CLK_N
cPCI J5, pin L6
Output
PE8_CLK_P
cPCI J5, pin K6
OUT8
PE7_CLK_N
cPCI J5, pin I6
Output
PE7_CLK_P
cPCI J5, pin H6
OUT9
CLK9_P
Clock Driver LTC6975 U73
Output
reference clock input to dual clock driver U73
CLK9_N
XA/XB
XAXB_P
54.000 MHz quartz oscillator Y3
Input
Differential quartz oscillator clock input
XAXB_N
SCLK, SDA/SDIO
I2C_SCL
I2C_SDA
MIO20
MIO21
BiDir
I²C address 0x69
The clock outputs OUT1 and OUT9 are distributed via clock buffer U16 and clock driver U14 to several PL and MGT banks:
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Table_OBP_clk_buffer
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Table 15: Clock driver and buffer outputs
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Si53340 U16 Pin
Signal Schematic Name
Connected to
Signal Direction
Note
Q0
CLK1_P
CLK1_N
U1, pin G8 U1, pin G7
Output
GTH bank 229 reference clock input
Q1
CLK2_P
CLK2_N
U1, pin Y8 U1, pin Y7
Output
PL HP bank 66 reference clock input
Q2
CLK3_P
CLK3_N
U1, pin U27 U1, pin U28
Output
PS GTR Bank 505 reference clock input
Q3
CLK4_P
CLK4_N
U1, pin L27 U1, pin L28
Output
GTH bank 129 reference clock input
LTC6957 U73 Pin
OUT1
CK_PLL_P
CK_PLL_N
U1, pin AG5 U1, pin AG4
Output
PL HP bank 65 reference clock input
OUT2
CK_P
CK_N
Signal 'SATA_SL' Signal 'SATA_SCL'
Output
optional reference clock input to cPCI connector J1, if decoupling capacitors and resistors are fitted (see schematic), also shared with SC FPGA and header J13
The clock generator U14 is programmable via the onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.
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Table_OBP_si5345_i2c
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Table 16: SI5345 I2C address
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I2C address
Chip
Description
0x69
U14 Si5345
Clock generator and distributor
...
The TEC0850 board is equipped several onboard oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the onboard peripherals with reference clock-signals:
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Table_OBP_osc
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Table 17: TEC0850 on-board oscillators
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Clock Source
Signal Schematic Name
Frequency
Clock Input Destination
SiTime SiT8008BI oscillator, U22
PS_CLK
33.333333 MHz
Zynq MPSoC U1 PS Config Bank 503, pin U24
SiTime SiT8008AI oscillator, U12
USB0_CLK
52.000000 MHz
USB2 transceiver PHY U11, pin 26
SiTime SiT8008AI oscillator, U16
OSCI
12.000000 MHz
FTDI FT2232H U4, pin 3
Kyocera CX3225SB30000, Y1
-
30.000 MHz
FTDI FT601Q U9, pin 21/22
CM-2012-2pad, Y2
-
32.768000 kHz
Zynq MPSoC U1 PS Config Bank 503, pin V21/V22
Kyocera CX3225SB26000, Y3
XAXB_P
XAXB_N
54.000 MHz
10-output PLL clock generator U14, pin 8/9
SiTime SiT8008BI oscillator, U21
ETH_CLKIN
25.000000 MHz
Gigabit Ethernet PHY U20, pin 34
ASVTX-12-A oscillator, U75
IN0_P
40.000 MHz
10-output PLL clock generator U14, pin 63
...
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Figure_OBP_ft2232
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Figure 17: TEC0850 on-board FTDI chips
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Channel B can be used as UART Interface routed to SC FPGA U18, 11 I/O's of Channel B is routed to are usable for example as GPIOs and other standard interfaces.
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Table_OBP_ft2232
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Table 18: FT2232H interface connections
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FT2232H U3 Pin
Signal Schematic Name
Connected to
Notes
Pin 12, ADBUS0
ADBUS0
SC FPGA U18 bank 6, pin G9
JTAG interface
Pin 13, ADBUS1
ADBUS1
SC FPGA U18 bank 6, pin F10
Pin 14, ADBUS2
ADBUS2
SC FPGA U18 bank 6, pin E10
Pin 15, ADBUS3
ADBUS3
SC FPGA U18 bank 6, pin D9
Pin 32, BDBUS0
BDBUS0
SC FPGA U18 bank 6, pin B11
UART and user configurable
GPIO's
Pin 33, BDBUS1
BDBUS1
SC FPGA U18 bank 6, pin A12
Pin 34, BDBUS2
BDBUS2
SC FPGA U18 bank 6, pin B12
Pin 35, BDBUS3
BDBUS3
SC FPGA U18 bank 6, pin C11
Pin 37, BDBUS4
BDBUS4
SC FPGA U18 bank 6, pin B13
Pin 38, BDBUS5
BDBUS5
SC FPGA U18 bank 6, pin C12
Pin 39, BDBUS6
BDBUS6
SC FPGA U18 bank 6, pin C13
Pin 40, BDBUS7
BDBUS7
SC FPGA U18 bank 6, pin D11
Pin 42, BCBUS0
BCBUS0
SC FPGA U18 bank 6, pin D12
Pin 46, BCBUS1
BCBUS1
SC FPGA U18 bank 6, pin E13
Pin 47, BCBUS2
BCBUS2
SC FPGA U18 bank 6, pin E12
Pin 48, BCBUS3
BCBUS3
SC FPGA U18 bank 6, pin F13
Pin 49, BCBUS4
BCBUS4
SC FPGA U18 bank 6, pin F12
Pin 11, nRESET
FTDI_RST
SC FPGA U18 bank 6, pin E9
control signals
...
The TEC0850 board is equipped with the FTDI FT601Q USB3 to 32bit-FIFO adapter controller connected to USB-C connector J10 to provide access to the Zynq MPSoC PL HP I/O's of bank 64. Also, 13 control signals of the FTDI FT601Q are connected to the HP bank 64.
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Table_OBP_ft601q
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Table 19: FT601Q interface connections
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FT601Q U9 Pin
Signal Schematic Name
Connected to
Notes
Pin 40, DATA0
DATA0
PL HP bank 64, pin AK1
user GPIO's
Pin 41, DATA1
DATA1
PL HP bank 64, pin AJ10
Pin 42, DATA2
DATA2
PL HP bank 64, pin AJ9
Pin 43, DATA3
DATA3
PL HP bank 64, pin AK7
Pin 44, DATA4
DATA4
PL HP bank 64, pin AK5
Pin 45, DATA5
DATA5
PL HP bank 64, pin AM1
Pin 46, DATA6
DATA6
PL HP bank 64, pin AL2
Pin 47, DATA7
DATA7
PL HP bank 64, pin AK4
Pin 50, DATA8
DATA8
PL HP bank 64, pin AN1
Pin 51, DATA9
DATA9
PL HP bank 64, pin AL3
Pin 52, DATA10
DATA10
PL HP bank 64, pin AK8
Pin 53, DATA11
DATA11
PL HP bank 64, pin AN2
Pin 54, DATA12
DATA12
PL HP bank 64, pin AP2
Pin 55, DATA13
DATA13
PL HP bank 64, pin AL7
Pin 56, DATA14
DATA14
PL HP bank 64, pin AL5
Pin 57, DATA15
DATA15
PL HP bank 64, pin AM4
Pin 60, DATA16
DATA16
PL HP bank 64, pin AN4
Pin 61, DATA17
DATA17
PL HP bank 64, pin AM5
Pin 62, DATA18
DATA18
PL HP bank 64, pin AM6
Pin 63, DATA19
DATA19
PL HP bank 64, pin AN3
Pin 64, DATA20
DATA20
PL HP bank 64, pin AP3
Pin 65, DATA21
DATA21
PL HP bank 64, pin AP4
Pin 66, DATA22
DATA22
PL HP bank 64, pin AP5
Pin 67, DATA23
DATA23
PL HP bank 64, pin AN6
Pin 69, DATA24
DATA24
PL HP bank 64, pin AN7
Pin 70, DATA25
DATA25
PL HP bank 64, pin AP6
Pin 71, DATA26
DATA26
PL HP bank 64, pin AP7
Pin 72, DATA27
DATA27
PL HP bank 64, pin AP11
Pin 73, DATA28
DATA28
PL HP bank 64, pin AP10
Pin 74, DATA29
DATA29
PL HP bank 64, pin AP9
Pin 75, DATA30
DATA30
PL HP bank 64, pin AN9
Pin 76, DATA31
DATA31
PL HP bank 64, pin AP8
Pin 58, CLK
FIFO_CLK
PL HP bank 64, pin AL6
control signals
Pin 4, BE0
BE_0
PL HP bank 64, pin AM10
Pin 5, BE1
BE_1
PL HP bank 64, pin AK10
Pin 6, BE2
BE_2
PL HP bank 64, pin AM11
Pin 7, BE3
BE_3
PL HP bank 64, pin AL11
Pin 13, nOE
OE_N
PL HP bank 64, pin AL8
Pin 12, nRD
RD_N
PL HP bank 64, pin AK9
Pin 11, nWR
WR_N
PL HP bank 64, pin AM9
Pin 8, nTXE
TXE_N
PL HP bank 64, pin AK12
Pin 9, nRXN
RXF_N
PL HP bank 64, pin AJ12
Pin 10, nSIWU
SIWU_N
PL HP bank 64, pin AL10
Pin 15, nRESET
FTDI_RESET_N
PL HP bank 64, pin AM8
Pin 16, nWAKEUP
WAKEUP_N
PL HP bank 64, pin AN8
...
On-board QSPI flash memory U24 and U25 on the TEC0850 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each, 64 MByte total QSPI Flash memory. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC, enabling dual parallel booting from QSPI Flash memory. This nonvolatile memory is used to store an initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
The EEPROMs U63 and U64 are programmable via the onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.
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Table 21: EEPROMs I²C Addresses
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I2C address
Chip
Description
0x50
U63 24AA128T-I/ST
128K Serial EEPROM
0x53
U64 24AA025E48T-I/OT
2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity
...
USB2 PHY U11 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator U12. There is also the option to equip the TEC0850 board with a second USB2 PHY U13 connected to the optional cPCI backplane connector J3. Both, the optional USB2 PHY U13 and cPCI connector J3 are not fitted by default.
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Figure 20: TEC0850 cPCI USB2 interface
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Table 22: USB2 ULPI interface description
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USB2 PHY U11 Pin
Connected to
Notes
ULPI
PS bank MIO52 ... MIO63
Zynq Ultrascale+ USB0 MIO pins are connected to the PHY
REFCLK
-
52MHz from onboard oscillator U12
REFSEL[0..2]
-
All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETB
Zynq MPSoC MIO16, pin AM16
Low active USB2 PHY Reset
DP, DM
cPCI connector J1
USB2 data lane
CPEN
-
External USB power switch active-high enable signal
VBUS
5V
Connected to onboard 5V voltage level via a series of resistors, see schematic
ID
3.3V
USB2 OTG A-Device (host)
optional USB2 PHY U13 Pin
Connected to
Notes
ULPI
PS bank MIO64 ... MIO75
Zynq Ultrascale+ USB1 MIO pins are connected to the PHY
REFCLK
-
52MHz from onboard oscillator U12
REFSEL[0..2]
-
All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETB
Zynq MPSoC MIO17, pin AP16
Low active USB2 PHY Reset
DP, DM
optional cPCI connector J3
USB2 data lane
CPEN
-
External USB power switch active-high enable signal
VBUS
5V
Connected to onboard 5V voltage level via a series of resistors, see schematic
ID
3.3V
USB2 OTG A-Device (host)
...
Onboard Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512, which use MDIO address 1. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21.
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Figure 21: TEC0850 GbE interface with RJ-45 MegJack
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The TEC0850 Board has 4 8-bit parallel Texas Instruments THS5641AIPW digital to analog converter (DAC) with up to 100 MSPS update rate connected to TI THS4631D operational amplifiers. See Schematic circuitry and TI THS5641 data sheet for proper operation of the on-board DAC units.
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Table 23: DAC units interface description
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DAC unit
Signal Schematic Name
Connected to
Functionality
DAC1
U28
DAC1_D0
PL HD bank 50, pin D11
Digital input bits D[7:0]
D7 is the most significant data bit (MSB), D0 is the least significant data bit (LSB).
DAC1_D1
PL HD bank 50, pin D10
DAC1_D2
PL HD bank 50, pin G11
DAC1_D3
PL HD bank 50, pin J11
DAC1_D4
PL HD bank 50, pin G10
DAC1_D5
PL HD bank 50, pin H10
DAC1_D6
PL HD bank 50, pin J10
DAC1_D7
PL HD bank 50, pin E10
DAC1_CLK
PL HD bank 50, pin F12
External clock input, input data latched on rising edge of the clock.
DAC1_MODE
PL HD bank 50, pin F10
Input code format (binary, twos complement)
EN_DAC1
SC FPGA U18 bank 8, pinE6
generate 3.3V voltages LDO U35, U34
DAC2
U31
DAC2_D0
PL HD bank 50, pin G15
Digital input bits D[7:0]
D7 is the most significant data bit (MSB), D0 is the least significant data bit (LSB).
DAC2_D1
PL HD bank 50, pin H14
DAC2_D2
PL HD bank 50, pin J14
DAC2_D3
PL HD bank 50, pin G14
DAC2_D4
PL HD bank 50, pin G13
DAC2_D5
PL HD bank 50, pin H13
DAC2_D6
PL HD bank 50, pin H12
DAC2_D7
PL HD bank 50, pin J12
DAC2_CLK
PL HD bank 50, pin F12
External clock input, input data latched on rising edge of the clock.
DAC2_MODE
PL HD bank 50, pin F11
Input code format (binary, twos complement)
EN_DAC2
SC FPGA U18 bank 8, pin E8
generate 3.3V voltages LDO U32, U60
DAC3
U29
DAC3_D0
PL HD bank 44, pin AG14
Digital input bits D[7:0]
D7 is the most significant data bit (MSB), D0 is the least significant data bit (LSB).
DAC3_D1
PL HD bank 44, pin AE13
DAC3_D2
PL HD bank 44, pin AG13
DAC3_D3
PL HD bank 44, pin AJ15
DAC3_D4
PL HD bank 44, pin AJ14
DAC3_D5
PL HD bank 44, pin AH14
DAC3_D6
PL HD bank 44, pin AL13
DAC3_D7
PL HD bank 44, pin AM13
DAC3_CLK
PL HD bank 44, pin AK15
External clock input, input data latched on rising edge of the clock.
DAC3_MODE
PL HD bank 44, pin AK14
Input code format (binary, twos complement)
EN_DAC3
SC FPGA U18 bank 8, pin B6
generate 3.3V voltages LDO U66, U68
DAC4
U33
DAC4_D0
PL HD bank 44, pin AP14
Digital input bits D[7:0]
D7 is the most significant data bit (MSB), D0 is the least significant data bit (LSB).
DAC4_D1
PL HD bank 44, pin AN14
DAC4_D2
PL HD bank 44, pin AM14
DAC4_D3
PL HD bank 44, pin AN13
DAC4_D4
PL HD bank 44, pin AP12
DAC4_D5
PL HD bank 44, pin AN12
DAC4_D6
PL HD bank 44, pin AF13
DAC4_D7
PL HD bank 44, pin AH13
DAC4_CLK
PL HD bank 44, pin AK13
External clock input, input data latched on rising edge of the clock.
DAC4_MODE
PL HD bank 44, pin AK13
Input code format (binary, twos complement)
EN_DAC4
SC FPGA U18 bank 8, pin A6
generate 3.3V voltages LDO U70, U72
...
The table below describes the functionalities of the switches of DIP-switches S1 and S2 at their every position:
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