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id | Comments |
Important General Note:
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Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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Figure template:
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title | Text |
Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table template:
- Layout macro can be use for landscape of large tables
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anchor | Table_tablename |
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title | Text |
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The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
<type>_<main section>_<name>
- type: Figure, Table
- main section:
- "OV" for Overview
- "SIP" for Signal Interfaces and Pins,
- "OBP" for On board Peripherals,
- "PWR" for Power and Power-On Sequence,
- "B2B" for Board to Board Connector,
- "TS" for Technical Specification
- "VCP" for Variants Currently in Production
- "RH" for Revision History
- name: custom, some fix names, see below
- Fix names:
"Figure_OV_BD" for Block Diagram
"Figure_OV_MC" for Main Components
"Table_OV_IDS" for Initial Delivery State
"Table_PWR_PC" for Power Consumption
- "Figure_PWR_PD" for Power Distribution
- "Figure_PWR_PS" for Power Sequence
- "Figure_PWR_PM" for Power Monitoring
- "Table_PWR_PR" for Power Rails
- "Table_PWR_BV" for Bank Voltages
"Table_TS_AMR" for Absolute_Maximum_Ratings
"Table_TS_ROC" for Recommended_Operating_Conditions
- "Figure_TS_PD" for Physical_Dimensions
- "Table_VCP_SO" for TE_Shop_Overview
"Table_RH_HRH" for Hardware_Revision_History
- "Figure_RH_HRN" for Hardware_Revision_Number
- "Table_RH_DCH" for Document_Change_History
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Note for Download Link of the Scroll ignore macro:
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Table of Contents
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Overview
The Trenz Electronic TE0835 is an extended-grade module based on Xilinx UltraScale+ RFSoC.
Refer to http://trenz.org/te0835-info for the current online version of this manual and other available documentation.
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Notes :
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Key Features
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id | Comments |
Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options
Key Features' must be split into 6 main groups for modules and mainboards:
- SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- size:*
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- Low Power DDR4 on PS
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- 4 cm x 5 cm
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier:
- Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- E.g. SDRAM, SPI
- On Board
- E.g. CPLD, PLL
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
- SoC/FPGA
- Xilinx UltraScale+ RFSoC (XCZU25DR-1FFVE1156E)
- Package: E1156
- Speed: -1 (slowest)
- Temperature: Extended (0 to +100 °C)
- Xilinx UltraScale+ RFSoC (XCZU25DR-1FFVE1156E)
- RAM/Storage
- 4x 8Gb DDR4
- 2x 512Mb SPI Flash
- 2k I2C EEPROM
- On Board
- Lattice MachXO2 CPLD
- Programmable Clock Generator
- 3x Oscillators
- Interface
- 2x Samtec ST5 (2x80 pol) Board to Board Connectors
- Power
- 5V Input Supply Voltage
- Dimension
- 90 x 65 mm
Block Diagram
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id | Comments |
add drawIO object here.
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For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" . |
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anchor | Figure_OV_BD |
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title | TE0835 block diagram |
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Main Components
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id | Comments |
Notes :
- Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" . |
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anchor | Figure_OV_MC |
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title | TE0835 main components |
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- Xilinx UltraScale+ RFSoC XCZU25DR, U1
- 8Gb DDR4 SDRAM, U2,U3,U5,U9
- Voltage Regulators, U4,U6,U7
- Programmable Glock Generator, U15
- Lattice MachXO2 CPLD, U31
- Dual SPI Flash, U24-U25
- USB2.0 Transceiver, U11
- Pin Header 3x1, J3 (not Soldered)
- Gigabit Ethernet Transceiver, U20
- EEPROM, U23
- B2B Connector, J2
- B2B Connector, J1
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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Storage device name
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Content
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Notes
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2x SPI Flash
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Configuration Signals
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MODE[0:3]
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0000
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PS_JTAG
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anchor | Table_OV_RST |
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title | Reset process. |
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Signal
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RESETN
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Notes :
- For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- SD
- USB
- ETH
- FMC
- ...
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
- JTAG
- UART
- I2C
- MGT
- ...
Board to Board (B2B) I/Os
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JTAG access to the TE0835 is through B2B connector JM1.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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JTAG Signal
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B2B Connector
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J1-22
MIO Pins
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id | Comments |
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
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SPI_CS , SPI_DQ0... SPI_DQ3
SPI_SCK
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UART_TX, UART_RX
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Test Points
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id | Comments |
you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
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anchor | Table_SIP_TPs |
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title | Test Points Information |
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B2B, J1
CPLD, U31
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B2B, J1
CPLD, U31
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B2B, J1
CPLD, U31
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B2B, J1
CPLD, U31
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B2B, J1
CPLD, U31
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IO_L1P_AD15P_88,
O_L4N_AD12N_88
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EEPROM,U23
FPGA Bank 501, U1
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Notes :
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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anchor | Table_OBP |
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title | On board peripherals |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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USB2.0
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Ethernet
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MDI0...3
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EEPROM
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LEDs
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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DDR4 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0835 SoM has 4x 1 Gigabyte volatile DDR4 SDRAM IC for storing user application code and data.
- Part number: K4A8G165WB
- Supply voltage: 1.2 V
Speed: 2400 Mbps
Temperature: -40 ~ 95 °C
Clock Sources
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anchor | Table_OBP_CLK |
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title | Osillators |
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Voltage Monitor Circuit
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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JM1 Pin
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B2B Connector
JM2 Pin
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B2B Connector
JM3 Pin
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Bank Voltages
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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Bank
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Voltage
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