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This step guides through the tasks which have to be done inside Intel Quartus Prime. As mentionend in page "Board bring-up overview for TEI0022", this step is for project generation, system setting and output creation. Therefore, the work within this step should be explained in three sections:
- Project Creation
- System Setting
- Output Creation
The section "Project Creation" describes the basic work to create a new project. The second section "System Setting" explains the creation of an HPS instance inside the project. And the third section "Output Creation" shows how to create the result output inside Intel Quartus Prime.
Project Creation
This section guides through the project creation:
Achtung beim Schritt HDL generate
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USB Controllers
SPI Controllers
Enable MPU Interrupts auswählen, dann muss das verbunden werden oder Exportiert, wohin / womit?
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The project wizard of Quartus lite guides through the setup of a project.
Before using it, it is suggested to create a project directory for storing it via a file browser.
Quartus lite does not create a folder for you. The generation of the bootloaders requires a
SoC EDS Shell with root privileges on a windows systems. Their file system access
is limited to the C drive. Therefore it is best practice for Windows users to store the project
on the C drive.
In essence, the project setup consists pointing to the project directory, naming the project,
and adding a device to it.
This guide uses the folder Project and the project itself is named HPSexample.
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- Start Intel Quartus Prime
- Select:
- File → New Project Wizard...
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In the following windows - Project Type - and - Add Files - is nothing further required other
than clicking Next.
In the next window - Family, Device & Board Settings - it is required to select either a
FPGA Device or a Board from the List.
Copy 5CSEMA5F31C8(N) into the field Name filter , this reduces the Device list, and select it in the list.
In the window EDA Tool Settings just click Next and Finish in the following window - Summary.
Quartus places the folder db, two files HPSexample.qpf and HPSexample.qsf into the project folder
and the setup is accomplished.
Plattform Designer
This program generates the files needed to connect and configures the HPS so that it gets connected to the physical board resources.
The basic storage resources the HPS needs are System Memory and SD card access, to communicate the basic interfaces are Uart and i²c.
These files are:
- HPSexample.sopinfo - describes all of the components and connections in your system and
parameterization of each component in the system
- PlattformEditorHPS.qip - The contains paths for all of the files for an IP core
- (hps_isw_)handoff folder - Folder containing general and SoC / board specific source files for generating the bootloaders
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File → New , select Qsys System File and press OK, the Plattform Designer opens in a new window.
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Now, the following figure should be visible:
- Click Next >
- Select the project folder and the project name (e.g. HPSexample). Then, click Next >
- Select an "Empty project" and click Next > in the window "Project Type"
- Click Next > in the window "Add Files"
- Select the used FPGA in the window "Family, Device & Board Settings". For the board TEI0022, copy "5CSEMA5F31C8(N)" into the field "Name filter", select the "5CSEMA5F31C8(N)" SoC and click Next >.
- Click Next > in the window "EDA Tool Settings"
- Click Finish in the window "Summary"
- The Intel Quartus project is generated and the folder should look like the next figure.
System Setting
This section guides through the system setting with the Plattform Designer to generate and configure the HPS according to the physical board resources.
- Create a Plattform Designer file: File → New
- Select "Qsys System File" and press "OK"
- A new window should open.
- Look for "hps" inside the search field, as visible in the following figure.
- Select "Arria V/Cyclone V Hard Processor System" via double click from the tree:
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- Library → Processors and
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- Peripherals → Hard Processor
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- Systems → Arria V/Cyclone V Hard Processor System
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- The window
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- "Arria V/Cyclone V Hard Processor System - hps_0
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- " should be opened as visible in the next figure.
- In this window the HPS has to be configured with the following settings:
- Tab FPGA Interface:
- Uncheck "Enable MPU standby and event signals" (default)
AXI Bridges:
FPGA-to-HPS interface width:
- Tab FPGA Interface:
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Unused
HPS-to-FPGA interface width:
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Unused
Lightweight HPS-to-FPGA interface width:
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Unused
- Tab Peripheral Pins:
- Quad SPI Flash Controller
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- → QSPI pin: HPS I/O Set 0
- SD/MMC Controller
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- → SDIO pin: HPS I/O Set 0
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- → SDIO mode: 4-bit Data
- UART Controllers
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- → UART0 pin: HPS I/O Set 0
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- → UART0 mode: no Flow Control
- I2C Controllers
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- → I2C0 pin: HPS I/O Set 1
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- → I2C1 pin: HPS I/O Set 0
- Tab HPS Clocks:
- As is / Accept the default values (for both subtabs)
- Tab SDRAM
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- Subtab Phy Settings:
- Memory clock frequency: 333.3 MHz
- PLL reference clock frequency: 25 MHz
- Subtab Phy Settings:
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Subtab - Memory Parameters:
Memory device speed grade: 800.0 MHz
Total interface width: 32
Row Address width: 16
Column Address width: 10
- Memory Initialization Options
Memory CAS latency setting: 5
ODT Rtt nominal value: RZQ/6
Memory write CAS latency settings: 5
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- Subtab - Memory Timing:
- tIS (base): 180
- Subtab - Memory Timing:
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- ps
- tIH (base): 140 ps
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- tDS (base): 30 ps
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- tDH (base):
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- 65
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- ps
- tDQSQ: 100
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- ps
- tQH: 0.38
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- cycles
- tDQSCK
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- : 225 ps
- tDQSS: 0.27 cycles
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- tQSH: 0.4
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- cycles
- tDSH: 0.18
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- cycles
- tDSS: 0.18
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- cycles
- tINIT: 500
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- us
- tMRD (tMRW): 4
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- cycles
- tRAS: 35.0
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- ns
- tRCD: 13.75
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- ns
- tRP: 13.75
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- ns
- tREFI (tREFIab): 7.8
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- us
- tRFC (tRFCab): 350.0
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- ns
- tWR: 15.0 ns
- tWTR: 4
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- cycles
- tFAW: 40
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- ns
- tRRD: 12.0
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- ns
- tRTP: 12.0 n
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Subtab - Board Settings:
Board Skews
Maximum CK delay to DIMM/device: 0.03
Maximum
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DQS delay to DIMM/device: 0.02
Minimum delay difference between CK and DQS:
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0.09
Maximum
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delay difference between CK and DQS:
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0.16
Maximum skew within DQS group: 0.01
Maximum skew between DQS groups: 0.08
Maximum skew within address and command bus:
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0.03
- Click "Finish
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- " to close the window
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- "Arria V/Cyclone V Hard Processor System - hps_0
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- ".
Add connections via clicking into the circle marked with a red rectangle in
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the next figure:
hps_0 - h2f_reset → clk_0 - clk_in_reset
clk_0 - clk → hps_0 - f2h_sdram0_data
- The HPS is nearly
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- configured. Apply some auto functions:
System → Assign Base Addresses
System → Assign Interrupt Numbers
System → Assign Custom Instruction Opcodes
System → Create Global Reset Network
Achtung beim Schritt HDL generate
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- Click Generate HDL... to generate the hardware description language file.
- Window "Generation" opens.
- In this window, under "Synthesis", select via
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- dropdown menu in which
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- Hardware Language your HDL will be created, Verilog or VHDL,
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- Uncheck Create timing and resource estimate... .
- Check Create block symbole file (.bsf).
Press in the bottom left Generate and a saving dialogue opens, reminding to save the design. Name the file, this
guide designates the file PlatformEditorHPS.qsys , press Save and wait until the design is saved. The window shows
the message - Save System: Completed successfully.
Press Close and immediately a new window opens, in it press Generate and wait for the
message - Generation: Completed successfully - to show up, press Close to shut the window down.
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- Click Generate, as visible in the next figure.
- Save the changes according to the opened saving dialogue, which is shown in the next figure.
- Name the file (e.g. PlatformEditorHPS.qsys) and press Save, as visible in the next figure.
- After saving, the message "Save System: Completed successfully." should be shown and the view should be similar to the next figure.
- Press Close.
- Wait until the generation is finished and the message "Generation: Completed successfully." is shown according to the next figure.
- Press Close.
- Leave the Plattform Designer by pressing Finish.
- A notification appears, reminding to add files into the project,
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- press OK.
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Close the Plattform Designer by pressing Finish.
Output Creation
This section guides through the output creation:
- Add the file "PlatformEditorHPS.qsys" to the project by using Project → Add/Remove Files in Project ..
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- .
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Click onto the button with three dots (inside the red rectangle) in the opened window as visible in the next figure.
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- In the "Select File
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- " window select the file ... > PlatformEditorHPS → synthesis → PlatformEditorHPS.qip
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- .
- Click OK.
- Change the view from "Hierarchy" to "Files" inside the drop-down menu withing the "Project Navigator".
- Set file "PlatformEditorHPS.qip" as top-level entity by right clicking onto the file and selecting
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- Set as Top-Level Entity.
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- Select Tools → Tcl Scripts...
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- Select Project
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- → PlatformEditorHPS → synthesis → submodules → hps_sdram_p0_pin_assignments.
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- tcl and click Run
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- .
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- Confirm the notification and close the previous window through
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- Close.
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- Press Processing → Start
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- Compilation
- Compilation process has to be finished without errors. Fix errors if there are some.
- The project folder should look like the following figure.
After this doing this guide, following files and folders are generated with the given purpose which are relevant for the next guide.
| File/Folder | Purpose |
|---|---|
| .sopcinfo | SOPC Info File containing hardware description for the Device Tree Generator |
| hps_isw_handoff | Folder containing a hardware description for the Preloader Generator |
Now the project folder contains the following.
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