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Overview

The Trenz Electronic TE0821 is a powerful 4 x 5 cm SoM integrating an AMD Zynq UltraScale+ MP-SoC. In addition, the module is equipped with two DDR4 SDRAM chip for up to 4 GByte, up to 64 GB eMMC chip, two 64 MByte QSPI Flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. The module is equipped with a system controller (Lattice Mach XO2). Three robust high-speed B2B connectors provide a large number of IOs.

Refer to http://trenz.org/te0821-info for current online available documentation.

Key Features

  • SoC
    • AMD Zynq UltraScale+ MPSoC:
    • Device:                      XCZU2 / XCZU3 / XCZU3T / XCZU4 / XCZU5 1)
    • Engine:                      CG / EG / EV 1)
    • Speedgrade:              -1 / -2 / -3 / -1L / -2L 1)
    • Temperature Range:  I / E 1) 
    • Package:                    SFVC784
  • RAM/Storage
    • 2 x 2 GByte DDR4 SDRAM 1)
    • 2 x 64 MByte QSPI Flash for Zynqs Dual Parallel Mode
    • 8 GByte eMMC Memory 1)
    • Serial EEPROM with EUI-48™ ID / MAC address
  • On Board
    • System Controller
    • 10/100/1000 BASE-T Ethernet PHY
    • USB 2.0 ULPI Transceiver with OTG support
    • Programmable Clock Generator
    • Reset Controller
    • Voltage Supervisor
    • LEDs:
      • 1 x user green
      • 3 x status green and red
  • Interface
    • Trenz 4 x 5 SoM 3 x B2B Connector (Samtec LSHM) socket:
      • MIO:     14 x SE
      • HD IO:  96 x SE / 48x DIFF
      • HP IO:  34 x SE / 17x DIFF
      • MGT:    4 x GTR and 1x CLK
  • Power
    • Single supply operation possible
    • All power regulators on board
  • Dimension
    • 40 mm x 50 mm
  • Note
    1) Depends on assembly variant.

Block Diagram

TE0821 block diagram

Main Components


TE0821 main components
  1. AMD ZYNQ UltraScale+ MPSoC, U1
  2. DDR4 SDRAM, U2, U3
  3. QSPI Flash, U7, U17
  4. eMMC Memory, U6
  5. EEPROM, U25
  6. Programmable Clock Generator, U10
  7. Oscillators, U11, U14, U32
  8. Ethernet Transceiver, U8
  9. USB 2.0 Transceiver, U18
  10. System Controller, U21
  11. LED ERR_OUT (red), D3
  12. LED ERR_STATUS (green), D4
  13. LED DONE (red), D1
  14. LED user (green), D2
  15. B2B connector (Samtec LSHM), JM1, JM2, JM3

Initial Delivery State

Storage device name

Content

Notes

Dual QSPI Flash Memory

Not programmed


eMMC Memory

Not programmed


DDR4 SDRAM

Not programmed


Programmable Clock Generator

Not programmed


System Controller

Firmware

Refer to TE0821 CPLD Firmware / TE0821 CPLD / TE0821-01-REV01 CPLD for more information.

Initial delivery state of programmable devices on the module

Signals, Interfaces and Pins

Connectors 1)

Connector Type

Designator

Interface

IO CNT

Notes

B2B

JM1

IO HD

24x SE / 12x DIFF

Bank 25

B2B

JM1

IO HD

24x SE / 12x DIFF

Bank 26

B2B

JM2

IO HD

24x SE / 12x DIFF

Bank 24 2)

B2B

JM2

IO HD

24x SE / 12x DIFF

Bank 44

B2B

JM2

IO HP

18x SE / 9x DIFF

Bank 65

B2B

JM3

IO HP

16x SE / 8x DIFF

Bank 65

B2B

JM1

MIO

8x SE

Bank 501

B2B

JM1

MIO / SDIO

6x SE

Bank 501

B2B

JM3

MGT

4x GTR

Bank 505

B2B

JM3

MGT CLK

1x DIFF

Bank 505

B2B

JM1

ETH MDI

4x DIFF


B2B

JM3

ETH SGMII

2x DIFF


B2B

JM3

USB 2.0

3x Se + 1x DIFF

Bus voltage, control and data

B2B

JM3

CLK in

1x DIFF

Clock Generator

1) Refer to 4 x 5 SoM Integration Guide for more information regarding 4 x 5 SoM compatibility.

2) TE0820 and TE0823 have two more IOs at connector JM2 (JM2 - pin 89 and JM2 - pin 100).

Board Connectors


Test Points

Test Point

Top

Bottom

Signal

Notes

TP1


x

I2C_SCL


TP2


x

I2C_SDA


TP3


x

SRST_B


TP4


x

PS_CLK


TP5


x

PROG_B


TP6


x

INIT_B


TP7


x

DONE


TP8


x

PS_LP0V85


TP9


x

DDR_2V5


TP10


x

PS_MGTRAVCC


TP11


x

DDR_1V2


TP12


x

PS_MGTRAVTT


TP13


x

PS_FP0V85


TP14


x

POR_B


TP15


x

PS_PLL


TP16


x

PL_VCCINT


TP17


x

DDR4-TEN


TP18


x

AVDD18


TP19


x

PL_VCCINT_IO


TP20


x

PL_VCU


TP21


x

DVDD1V


TP22


x

VTT


TP23

x


VREFA


TP24

x


PS_PLL


TP25

x


PG_ALL



Test Points Information

On-board Peripherals

Chip/InterfaceDesignatorConnected ToNotes

AMD Zynq UltraScale+ MP-SoC

U1
  • DDR4 SDRAM
  • QSPI Flash
  • eMMC
  • Programmable Clock Generator
  • Ethernet PHY
  • EEPROM with MAC
  • USB 2.0 PHY
  • Oscillator U32
  • LEDs status
  • B2B Connector

DDR4 SDRAM

U2 / U3
  • SoC

QSPI Flash

U7 / U17
  • SoC

eMMC

U6
  • SoC

System Controller

U21
  • SoC
  • LED user
  • B2B Connector

Refer to TE0821 CPLD Firmware / TE0821 CPLD / TE0821-01-REV01 CPLD for more information.

Programmable Clock Generator

U10
  • SoC / I2C
  • Oscillator U11
  • B2B Connector

Ethernet PHY

U8
  • SoC
  • Oscillator U11
  • B2B Connector

EEPROM with MAC

U25
  • SoC / I2C

USB 2.0 PHY

U18
  • SoC
  • Oscillator U14

Oscillator

U32
  • SoC
33⅓ MHz
OscillatorU11
  • Programmable Clock generator
  • Ethernet PHY
25 MHz
OscillatorU14
  • USB 2.0 PHY
52 MHz
On board peripherals

Configuration and System Control Signals

Signal Name

Connector.Pin

Direction 1)

Description

EN

JM1.28

IN

Power Enable Pin.  Firmware dependent, when R113 is populated 2). In default assembly variants R113 is unpopulated.

PGOOD

JM1.30

INOUT

PGOOD Pin. Firmware dependent 2)

MODE

JM1.32

IN

ZynqMP Boot Mode Pin 0. Firmware dependent 2)

NOSEQ

JM1.7

INOUT

No Sequencing. Firmware dependent 2)

MR

JM2.18

IN

Manuel reset

JTAGEN

JM1.89

IN

Select JTAG access between FPGA or System Controller. Firmware dependent 2)

JTAG (C_TMS / C_TDI / C_TDO / C_TCK)

JM2.93 / JM2.95 / JM2.97 / JM2.99

Signal dependent

JTAG interface

1) Direction:

    • IN: Input from the point of view of this board.

    • OUT: Output from the point of view of this board.

    • INOUT: Bidrectional signal.
    • Signal dependent: A Signal can have different functions and directions as part of a Bus.

2) For further information see TE0821 CPLD Firmware / TE0821 CPLD / TE0821-01-REV01 CPLD.

Controller signal.

Power and Power-On Sequence

Power Rails

Power Rail Name / Schematic Name

Connector.Pin

Direction 1)

Notes

VIN

JM2.2 / JM2.4 / JM2.6 / JM2.8 / JM1.1 / JM1.3 / JM1.5

IN


3.3VIN

JM2.91 / JM1.13 / JM1.15

IN


PSBATT

JM1.79

IN


VCCO_65

JM2.5

IN


VCCO_HD25_26

JM1.9 / JM1.11

IN/OUT 2)

On request this bank voltage can be supplied from 3.3 V
via resistor R89 which is not assembled in default state.

VCCO_HD24_44

JM2.7 / JM2.9

IN/OUT 3)

On request this bank voltage can be supplied from 3.3 V
via resistor R6 which is not assembled in default state.

3.3V

JM2.10 / JM2.12

OUT


1.8V

JM1.39

OUT


1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.

2) If resistor R89 is assembled do not supply this power rail externally because these connector pins are outputs.

3) If resistor R6 is assembled do not supply this power rail externally because these connector pins are outputs.

Module power rails.

Recommended Power up Sequencing


SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes
0---

Setup configuration SoM signals.

See Configuration and System Control Signals.

1

VIN

3.3 V to 5.0 V ±5 %-Apply main SoM supply.Signal "EN" needs to be released.

3.3VIN

3.3 V ±5 %-Apply management SoM supply.
2

3.3V

--SoM generated output of 3.3V or 1.8V states external power supply can be delivered.Improved power up sequencing can be realized via system controller firmware. Refer to TE0821 CPLD Firmware / TE0821 CPLD / TE0821-01-REV01 CPLD for more firmware information.

1.8V

-
3

VCCO_HD_24_44

1.2 V to 3.3 V ±3 %-Apply SoC bank IO supplies.

VCCO_HD25_26

1.2 V to 3.3 V ±3 %-

VCCO_65

1.0 V to 1.8 V ±3 %-
Baseboard Design Hints

Board to Board Connectors

These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.

4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.

  • 2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
  • 1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)
Connector Mating height

When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height

Order numberConnector on baseboardcompatible toMating height
23836REF-189016-01LSHM-150-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-150-03.0-L-DV-A-S-K-TRLSHM-150-03.0-L-DV-A-S-K-TR7.0 mm
23838REF-189016-02LSHM-150-04.0-L-DV-A-S-K-TR8.0 mm

LSHM-150-06.0-L-DV-A-S-K-TRLSHM-150-06.0-L-DV-A-S-K-TR10.0mm
26125REF-189017-01LSHM-130-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-130-03.0-L-DV-A-S-K-TRLSHM-130-03.0-L-DV-A-S-K-TR7.0 mm
24903 REF-189017-02LSHM-130-04.0-L-DV-A-S-K-TR8.0 mm

LSHM-130-06.0-L-DV-A-S-K-TRLSHM-130-06.0-L-DV-A-S-K-TR10.0mm
Connectors.

The module can be manufactured using other connectors upon request.

Connector Speed Ratings

The LSHM connector speed rating depends on the stacking height; please see the following table:

Stacking heightSpeed rating
12 mm, Single-Ended7.5 GHz / 15 Gbps
12 mm, Differential

6.5 GHz / 13 Gbps

5 mm, Single-Ended11.5 GHz / 23 Gbps
5 mm, Differential7.0 GHz / 14 Gbps
Speed rating.
Current Rating

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Connector Mechanical Ratings
  • Shock: 100G, 6 ms Sine
  • Vibration: 7.5G random, 2 hours per axis, 3 axes total


Manufacturer Documentation

  File Modified
PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report Apr 07, 2016 by Thorsten Trenz
PDF File lshm_dv.pdf LSHM catalog page Apr 07, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing Apr 07, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing Apr 07, 2016 by Thorsten Trenz
PDF File REF-189016-01.pdf Technical Drawing Apr 07, 2016 by Thorsten Trenz
PDF File REF-189016-02.pdf Technical Drawing Apr 07, 2016 by Thorsten Trenz
PDF File REF-189017-01.pdf Technical Drawing Apr 07, 2016 by Thorsten Trenz
PDF File REF-189017-02.pdf Technical Drawing Apr 07, 2016 by Thorsten Trenz
PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report Apr 07, 2016 by Thorsten Trenz
PDF File tc0929--2611_qua(1).pdf Shock and vibration report Apr 07, 2016 by Thorsten Trenz



Technical Specifications

Absolute Maximum Ratings *)

Power Rail Name/ Schematic NameDescriptionMinMaxUnit

VIN

Main SoM supply

-0.3

7

V

3.3VIN

Managment supply-0.13.630V

PSBATT

Backup battery-0.52.0V

VCCO_65

IO supply-0.52.0V

VCCO_HD_25_26

IO supply-0.53.4V

VCCO_HD_24_44

IO supply-0.53.4V
Absolute maximum ratings

*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
   or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Temperature range

Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.

The categories are:

    Modules with commercial (C) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 70 °C.
    Modules with extended (E) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 85 °C.
    Modules with industrial (I) temperature grade are equipped with components that cover at least the ambient temperature range of -40 °C to 85 °C.

These categories do not take into account the entire custom system consisting of:

    Customer SoC design. The allowed main SoC temperature range is specified from the vendor by junction temperature using corresponding classes (C, E, I). See vendor documentation.
    Cooling solution, active and or passive cooling.
    Climate or environmental conditions besides ambient temperature range.
    Module orientation, neighbouring assemblies, neither other heat sources nor the SoC as heat source to other components.

Classification of the module can be looked up here: Article Number Information i.e.: TExxxx-xx-xx'I'xx, the 'I' indicates that all components are at least in Industrial temperature class.

The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.

Voltage rails

The following table aims to be generic for all variants. The voltage ranges are consistend across assembly variants, but exceptions are possible (custom request).

ParameterMinMaxUnitsReference Document

VIN

3.1356.0VSee schematic.

3.3VIN

3.1353.465 ≤ VINVSee schematic.

PSBATT

1.21.5VSee AMD DS925.

VCCO_65

0.971.854VSee AMD DS925.

VCCO_HD25_26

1.1643.399VSee AMD DS925.

VCCO_HD_24_44

1.1643.399VSee AMD DS925.
Recommended operating conditions.

Physical Dimensions

  • Module size: 40 mm × 50 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm.

  • PCB thickness: 1.745 mm ±10 %.

Physical Dimension

Currently Offered Variants 

Trenz shop TE0821 overview page*
English pageGerman page

*)  Module article name encoding table: Zynq Ultrascale+ based modules (MPSoC, RFSoC)

Trenz Electronic Shop Overview

Revision History

Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Board hardware revision number.


Date

Revision

Changes

Documentation Link

2024-11

REV02

  1. Q1 was changed from TPS27081ADDCR to MP5077GG-Z.
  2. R82 was removed.
  3. C143 and C144 were added.
  4. Signal trace lengths were changed. PCB routing was improved.
  5. D5 was added.
  6. Pins N9 (TEN) of U2A and U3A were connected together.
  7. R100 was added.
  8. U5 was changed from EN6363QI to MPM3860GQW-Z.
  9. U28 was added.
  10. Net "PG_ALL" was connected to pin 5 of CPLD U21.
  11. T2A and R113 - R115 were added (R113 DNP by default).
  12. Net "RST_EN" was connected to pin 27 of CPLD U21.
  13. Net EN was connected to pin 16 of U5 and pin 1 of U12.
  14. R116 and R117 were added (R116 DNP by default).
  15. All unconnected pins for Bank64 U1D were connected together.
  16. TP17, TP18, TP21, TP22 were added. Some testpoints were moved.
  17. C178 was added.
  18. R118 - R121 were added.
  19. C179 - C185 were added.
  20. C136, C140 were changed from 22u to 47u.
  21. C186, C187, C188, C189 were added.
  22. C15, C16 were changed from 4.7u to 10u.
  23. C48 was changed from 16V to 10V, C45 was changed from 4.7u to 10u.
  24. C49, C52, C53, C57 were changed from 4.7u to 10u.
  25. C2 was changed from 16V to 10V.
  26. C37, C41, C89, C94, C107, C130, C134 were changed from 16 V, 0603 to 10 V, 0402.
  27. FPGA speedgrade table was changed on page "POWER.SchDoc".
  28. C24, C25, C96, C110 were changed from 0805 to 0603.
  29. C19, C21, C23, C67, C84, C93, C129, C133, C135 were changed from 6.3 V to 10 V.
  30. C61 was changed from 16 V, 0402 to 6.3 V, 0201.
  31. Power Diagram page was added, System Overview was updated.
  32. Nets were renamed: "PS_AVCC" -> PS_MGTRAVCC, "PG_AVCC" -> PG_MGTRAVCC, "OTG-RCLK" -> OTG-REFCLK, "PS_AVTT" -> PS_MGTRAVTT, "PG_DDR" -> PG_DDR1V2.
  33. Connection for pin "SENSE" of U19 was changed from net PS_LP0V85 to net PS_FP0V85.
  34. Net PG_0V85 was connected to pin 1 (EN) of U27.
  35. Net "PG_PS_LP" was renamed to PG_PSLP_INTIO and connected with pin 2 (PG) of U27, pin 1 (EN) of U20 (instead net PG_0V85).
  36. Net PG_FP0V85 was created and connected to pin 2 (PG) of U26, pin 3 (EN) of U23 (instead net "PG_PS_LP") and pin 1 (EN) of U4 (instead net "PG_PS_LP")
  37. Net PG_DDR2V5 was created, pin 2 (PG) of U4 was connected to pin 1 (EN) of U9 (instead net "PG_PS_LP").
  38. R70 was unconnected from pin 1 of U9 and connected to pin 1 of U26.
  39. R122 was added.
  40. U11 was changed from SiT8008BI-73-XXS-25.000000E to SIT8008BI-73-18S-25.000000E.
  41. VDD for U10 and U11 was changed from 3.3V to 1.8V.

REV02

PCN

2019-04

2019-07

2021-08

2024-02

REV01

Initial Release

1.R38 value was changed to 20K (was: 40K2) to set VCU 0.9V

2. Change SPI Flash from N25Q512A11G1240E to MT25QU512ABB8E12-0SIT.
3. Change eMMC from MTFC4GACAJCN-4M IT to IS21ES08G-JCLI.

4. Change eMMC (U6) from IS21ES08G-JCLI / IS21ES64G-JCLI to SDINBDG4-8G-XI2 / SDINBDG4-64G-XI2.
5. Clock Revision Change (U11, U14) SiT8008AI-73-XXS-... to SiT8008BI-73-XXS-... .
6. Change Ferrite Beads (L1, L2, L3, L4, L5, L7, L9, L10, L11, L12) BKP0603HS121-T to MPZ0603S121HT000.
7. Set S/N to not fitted

8. Pull-up resistor (R82) removal for signal "MR".

REV01

PCN
PCN
PCN

Hardware Revision History



Document Change History

DateRevisionContributorDescription

  • Added additional notes for IO table.

2025-10-24

v.80

Kilian Jahn

  • Updated to TRM Template 4.3.2

2025-08-11

v.79

Maksim Tserabei

  • Overview changed: 4Gb up to 128 Gb eMMC -> 8GB up to 64 GB eMMC
    Key features RAM/Storage changed: Flash Size '512 Mb Gb' → '512 Mb', flash data width '8bit' → '4bit'
  • Key features RAM/Storage changed: eMMC Data Width: '16 Bit' → '8 Bit'
  • MGT Lanes connection table changed: duplicate RX2/TX2 fixed to RX3/TX3
  • Gigabit Ethernet table changed: MDIP0...3 → MDI0...3, S_IN → SIN, S_OUT → SOUT
  • eMMC flash memory point change: added SDINBDG4-8G-XI2 / SDINBDG4-8G-XI2 / SDINBDG4-8G-XI2
  • Board-to-Board B2B I/Os table changed: 15 I/O → 14 I/O
  • System controller CPLD table changed: RESIN row removed
  • USB Interface table changed: CPEN JM3 pin 17 → pin 53, USB_ID JM3 pin 23 → pin 51
  • MIO pins table changed: EEPROM, U25 → EEPROM, U25, PLL, U10; 63...77 Ethernet Transceiver, U8 → 64...77 Ethernet Transceiver, U8
  • On-board Peripherals changed: LEDs D1...3 → D1...4
  • Quad SPI Flash Memory table changed: WP/IO2 → nWP/IO2
  • DDR4 SDRAM point changed: 8Gb → 8Gb/16Gb, K4A8G165WB-BIRC → K4A8G165WB-BIRC / MT40A1G16TB-062E IT:F
  • Clock sources table changed: U32 80MHz → 33.333333MHz
  • Programmable clock generator point changed: 3 outputs connected to FPGA → 4 outputs connected to FPGA
  • Programmable clock generator table changed
  • Power distribution picture changed




  • Typos, 
  • added REV and Date in revision history table

v.73

Maksim Tserabei 

  • Note for EN signal in table "Reset process" changed
  • Table in chapter "System controller CPLD" changed: net EN1 changed to net EN_RST, net PG_ALL added
  • "Test points" table updated: TP17-TP25 added. Some test points renamed
  • "Power-On Sequence" figure updated

  • "Hardware Revision History" table updated

v.63

Martin Rohrmüller

  • bugfix boot mode
  • Corrected IO number in key features
2021-07-05v.61John Hartfiel
  • Update download Link

  • Update Change history
2021-06-07v.59Vadim Yunitski
  • Added missing text in Bank Voltages
  • Fixed typo in Bank Voltages
2020-07-15v.50Pedram Babakhani
  • Initial Release

--

all

  • --
Document change history.

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The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

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Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.






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