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The Trenz Electronic TE0745 is an AMD Zynq-7000 SoC based System on Module (SoM) which combines a dual core Arm Cortex-A9 MPCore and a FPGA with 125 k up to 350 k logic cells. The module integrates one SoC with up to two Quad GTP transceiver, DDR3L SDRAM, SPI Flash memory for configuration and operation, a Gigabit Ethernet PHY, a USB 2.0 PHY and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.
Refer to http://trenz.org/te0745-info for the current online version of this manual and other available documentation.
SoC
RAM/Storage
On Board
Interface
Power
3.3 V Power Supply
Dimension
52 mm x 76 mm
Notes
1) Assembly variant dependent.
2) Pin/Package-compatible sizes upon request.
Storage device name | Content | Notes |
|---|---|---|
Quad SPI Flash, U14 | Not programmed | |
EEPROM, U23 | Manufacturer programmed MAC | |
System Controller CPLD, U2 | Firmware programmed | Refer to TE0745 CPLD Firmware / TE0745 CPLD for more information. |
DDR3 SDRAM, U3, U5 | Not programmed | |
Programmable Clock Generator, U16 | Not programmed |
Connector Type | Designator | Interface | IO CNT | Notes |
|---|---|---|---|---|
| B2B | J3 | MGT GTX | 4x DIFF | |
| B2B | J1 | MGT GTX | 4x DIFF | Not available for SoC XCZC7030. |
| B2B | J1 | IO HR | 100x SE / 48x DIFF | Voltage range 1.2 V to 3.3 V. |
| B2B | J2 | IO HP | 100x SE / 48x DIFF | Voltage range 1.2 V to 1.8 V. |
| B2B | J3 | IO HP | 50x SE / 24x DIFF | Voltage range 1.2 V to 1.8 V. |
| B2B | J2 | IO MIO | 5x MIO | 1.8 V. Bank 500. |
| B2B | J3 | IO MIO | 12x MIO | 1.8 V. Bank 501. |
| B2B | J3 | MGT CLK IN | 2x DIFF / 1x DIFF | Only one available for SoC XCZC7030 |
| B2B | J3 | CLK GEN IN | 1x DIFF | |
| B2B | J3 | CLK GEN OUT | 2x DIFF | |
| B2B | J2 | ETH BASE-T | ETH | |
| B2B | J2 | USB OTG | USB | |
| B2B | J2 | I2C | 2x SE | 3.3V |
| B2B | J3 | ETH MDI | ETH MDI | |
| B2B | J1 | JTAG | JTAG |
Test Point | Signal | Notes |
|---|---|---|
TP1 | VCCINT | |
TP2 | VCCINT | |
TP3 | I2C_SCL | |
TP4 | I2C_SCL | |
TP5 | I2C_SDA | |
TP6 | I2C_SDA | |
TP7 | PL_1.8V | |
TP8 | PL_1.8V | |
TP9 | PS_VIN | |
TP10 | VCCPINT | |
TP11 | VCCPINT | |
TP12 | 1.35V | |
TP13 | 1.35V | |
TP14 | PS_1.8V | |
TP15 | PS_1.8V | |
TP16 | VTT | |
TP17 | VTT | |
TP18 | VTTREF | |
TP19 | VTTREF | |
TP20 | POR_B | |
TP21 | PL_VIN | |
TP22 | PL_GT_1V45 | |
TP23 | PL_GT_1V45 | |
TP24 | MGTAUX | |
TP25 | MGTAUX | |
TP26 | MGTAVTT | |
TP27 | MGTAVTT | |
TP28 | PL_GT_1V25 | |
TP29 | PL_GT_1V25 | |
TP30 | MGTAVCC | |
TP31 | MGTAVCC | |
TP32 | PS_3.3V | |
TP33 | VCCIO_12 | |
TP34 | VCCIO_13 | |
TP35 | VCCIO_34 | |
TP36 | VCCIO_35 | |
TP37 | VCCIO_33 | |
TP38 | VBAT_IN | |
TP39 | AVCC | |
TP40 | AVCC | |
TP41 | PWR_PL_OK | |
TP42 | PWR_PS_OK |
Chip/Interface | Designator | Connected To | Notes |
|---|---|---|---|
AMD Zynq 7000 SoC | U1 |
| |
DDR3 SDRAM | U3, U5 |
| |
QSPI Flash | U14 |
| |
Gbit Ethernet Transceiver | U7 |
| |
USB 2.0 ULPI Transceiver | U32 |
| |
System Controller | U2 |
| Refer to TE0745 CPLD Firmware / TE0745 CPLD for more information. |
Power Supervisor with Watchdog Timer for PS & PL voltage | U20, U22 |
| |
EEPROM with EUID/MAC | U23 |
| |
RTC | U24 |
| |
Programmable Clock Generator | U16 |
| |
Oscillator | U9 |
| 25 MHz |
| Oscillator | U12 |
| 33 ⅓ MHz |
| Oscillator | U21 |
| 25 MHz |
| Oscillator | U33 |
| 52 MHz |
Signal Name | Connector.Pin | Direction1) | Description |
|---|---|---|---|
| JTAG (TDI, TMS, TCK, TDO) | J1.142 / J1.144 / J1.143 / J1.145 | Signal dependent | JTAG configuration and debugging interface. JTAG reference voltage: PS_3.3V |
| JTAG_EN | J1.148 | IN | Select JTAG Target SoC or SC. |
| I2C (I2C_33_SCL, I2C_33_SDA) | J2.119 / J2. 121 | Signal dependent | 3.3V referenced I2C bus. |
| PS_SRST | J2.152 | IN | System reset signal. |
| RST_IN_N | J2.131 | IN | Main SoC reset signal |
| BOOTMODE | J2.133 | IN | Boot Mode selection. |
| PWR_PL_OK | J2.135 | OUT | Power good for SoC Programmable Logic (PL) |
| PWR_PS_OK | J2.139 | OUT | Power good for SoC Processing System (PS) |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
Power Rail Name/ Schematic Name | Connector.Pin | Direction1) | Notes |
|---|---|---|---|
| PS_VIN | J2.154 / J2.156 / J2.158 | IN | |
| PS_3.3V | J2.160 | IN | |
| PL_VIN | J1.147 / J1.149 / J1.151 / J1.153 / J1.155 / J1.157 / J1.159 | IN | |
| VBAT_IN | J1.146 | IN | |
| VCCIO_12 | J1.54 / J1.55 | IN | |
| VCCIO_13 | J1.112 / J1.113 | IN | |
| VCCIO_33 | J3.115 / J3.120 | IN | |
| VCCIO_34 | J2.29 / J2.30 | IN | |
| VCCIO_35 | J2.87 / J2.88 | IN | |
| PS_1.8V | J2.130 | OUT | |
| PL_1.8V | J3.84 / J3.85 | OUT |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
|---|---|---|---|---|---|
| 0 | - | - | - | Configuration signal setup. | |
| 1 | VBAT_IN | 1.8 V | - | Battery connection. | (optional) |
| 2 | PS_3.3V | 3.3 V | - | Management power supply. | |
| PS start-up | |||||
| 3 | PS_VIN | 3.3 V 1) | - | PS power supply. | Main module power supply for SoC PS. |
| 4 | PWR_PS_OK 2) | - | PU 3), PS_3.3V | PS power good status. | |
| PL start-up | |||||
| 3 | PL_VIN | 3.3 V 1) | - | PL power supply. | Main module power supply for SoC PL. |
| 4 | PWR_PL_OK 2) | - | PU 3), PS_3.3V | PL power good status. | |
| 5 | VCCIO_12 /VCCIO_13 | 1.14 V ... 3.465 V | - | Module HR IO bank voltages. | |
| 5 | VCCIO_33 /VCCIO_34 /VCCIO_35 | 1.14 V ... 1.89 V | - | Module HP IO bank voltages. | |
1) A higher or lower input voltage may be possible.
2) Firmware dependent. Refer to TE0745 CPLD Firmware / TE045 CPLD for more information.
3) (on module)
5.2 x 7.6 cm SoM Zynq carrier use three Samtec Razor Beam LP Socket Strip (SS5) on the top side.
This TRM is generic for all variants.
Variants of modules are described here: 7 Series Zynq-7000 based modules. Please contact us to inquire options.
Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
|---|---|---|---|---|
| PS_VIN | Micromodule Power (PS) | -0.3 | 7.0 | V |
| PS_3.3V | Micromodule Power | -0.3 | 3.6 | V |
| PL_VIN | Micromodule Power (PL) | -0.3 | 6.0 | V |
| VBAT_IN | RTC Power | -0.3 | 6.0 | V |
| VCCIO_12 | HR IO Bank power supply | -0.5 | 3.6 | V |
| VCCIO_13 | HR IO Bank power supply | -0.5 | 3.6 | V |
| VCCIO_33 | HP IO Bank power supply | -0.5 | 2.0 | V |
| VCCIO_34 | HP IO Bank power supply | -0.5 | 2.0 | V |
| VCCIO_35 | HP IO Bank power supply | -0.5 | 2.0 | V |
*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.
The categories are:
These categories do not take into account the entire custom system consisting of:
This SoM components are capable of being operated at industrial-grade temperatures, which cover at least the range of -40 °C to +85 °C.
The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components.
The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.
Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| PS_VIN | 3.135 | 3.465 | V | |
| PS_3.3V | 3.135 | 3.465 | V | |
| PL_VIN | 3.2 | 4.5 | V | |
| VBAT_IN | 1.8 | 3.3 | V | See RTC/ISL12020MIRZ datasheet. |
| VCCIO_12 | 1.14 | 3.465 | V | See SoC DS191 datasheet. |
| VCCIO_13 | 1.14 | 3.465 | V | See SoC DS191 datasheet. |
| VCCIO_33 | 1.14 | 1.89 | V | See SoC DS191 datasheet. |
| VCCIO_34 | 1.14 | 1.89 | V | See SoC DS191 datasheet. |
| VCCIO_35 | 1.14 | 1.89 | V | See SoC DS191 datasheet. |
Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm
PCB thickness: 1.6 mm ±10 %
All dimensions are shown in millimeters.
Trenz shop TE0745 overview page* | |
|---|---|
*) Module article name encoding table: 7 Series Zynq-7000 based modules
The hardware revision number is located on the PCB next to the module identifier, separated by a dash.
Date | Revision | Changes | Documentation Link |
|---|---|---|---|
| 2023-08 | 03 | 1. Removed serial number S/N. Connected U2 pin 20 to net "BOOTMODE". | |
| 2016-05 | 02 | 1. MAC EEPROM Address patch fixed on PCB 3. Change DDR3 RAM (U3, U5) from IM4G16D3FABG-125I to IS43TR16256BL-125KBLI. 7. Change SPI Flash from N25Q512A11G1240E to MT25QU512ABB8E12-0SIT 8. Change SPI Flash from N25Q256A11E1240E to N25Q512A11G1240E | |
| 2015-07 | 01 | Initial release |
| Date | Revision | Contributor | Description |
|---|---|---|---|
| |||
2025-06-09 | v.111 | Kilian Jahn |
|
2025-02-17 | v.106 | Martin Rohrmüller |
|
2022-11-17 | v.105 | John Hartfiel |
|
2021-10-18 | v.102 | Martin Rohrmüller |
|
2021-02-05 | v.98 | John Hartfiel |
|
2020-02-18 | v.94 | John Hartfiel |
|
| 2019-11-19 | v.93 | John Hartfiel |
|
| 2019-10-10 | v.92 | Pedram Babakhani |
|
| 2019-03-01 | v.83 | Pedram Babakhani |
|
| 2018-04-11 | v.81 | John Hartfiel |
|
| 2017-11-14 | v.80 | John Hartfiel |
|
| 2017-11-13 | v.79 | Ali Naseri, Jan Kumann, John Hartfiel |
|
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