This section describes how to configure the TE USB FX2 module and access some of its resources.
To program the firmware in the EEPROM, the IIC bus should be correctly configured.
To program the bitstream in the Flash, the SPI bus should be correctly configured.
See
for the files required.TE USB FX2 modules can be configured through a host computer with the following system requirements:
TE USB FX2 module type | Configuration mode connections |
---|---|
TE0300 | |
TE0320 | |
TE0630 |
TE USB FX2 module is equipped with a Cypress EZ-USB FX2 controller (TE USB FX2 microcontroller) to provide a high-speed USB 2.0 interface. Configuration of the TE USB FX2 module through a USB host is recommended for non-volatile on-site operations such as firmware upgrade or SPI Flash bitstream download.
Even when USB connector is used to program the FPGA image (aka FPGA bitstream), the SPI bus and the the SPI Flash memory are also used by C# OpenFutNet or Python Open_FUT.
The procedure followed by one of the two TE programs (or by a custom user program) is the following:
Even when USB connector is used to program the FX2 microcontroller's firmware, the IIC bus and the the IIC EEPROM memory are also used by C# OpenFutNet or Python Open_FUT.
The JTAG interface allows a
SPI interfaces allows a medium-fast (1-2 minutes), frequent and non-volatile configuration (SPI Flash bitstream download) of the TE0300 module (through J3 and direct SPI programming or TE USB FX2 microcontroller and OpenFutNet), TE0320 module (through B2B connection or TE USB FX2 microcontroller and OpenFutNet), TE0630 module (through TE USB FX2 microcontroller and OpenFutNet).
Through B2B interface JTAG (all TE USB FX2 modules) and/or SPI interface (TE0320 module only) could be used (see the two paragraphes above).
It is also possible to use B2B interface for
configurations.
The FX2 microcontroller uses 5 interfaces (see here):
The mode select pins, M[2:0] for Spartan-3E and Spartan-3A (M[1:0] for Spartan-6), define the configuration mode that the FPGA uses to load its bitstream, as shown in Table 2-1. The logic levels applied to the mode pins is sampled on the rising edge of INIT_B, immediately after the FPGA completes initializing its internal configuration memory. Functional Differences between Spartan-3 Generation Families summarizes the slight differences in functionality between the Spartan-3/6 generation families.
Spartan 6 FPGA Family | Spartan 3 FPGA Family | |||
---|---|---|---|---|
M[1:0] | Spartan-6 | M[2:0] | Spartan-3E | Spartan-3A DSP |
<0:1> | Master Serial/SPI Mode | <0:0:0> | Master Serial (Platform Flash) Mode (1) | |
<0:0:1> | Master SPI Mode | |||
<0:0> | Master SelectMAP/BPI (1) | <0:1:0> | BPI Up (1) | |
<0:1:1> | BPI Down (1) | Reserved | ||
It does not exist | <1:0:0> | Reserved | ||
<x:x> | JTAG Mode always available | <1:0:1> | JTAG Mode, | |
<1:0> | Slave Parallel (SelectMAP) Mode | <1:1:0> | Slave Parallel (SelectMAP) Mode | |
<1:1> | Slave Serial Mode | <1:1:1> | Slave Serial Mode |
(1) It is a mode not available in TE USB FX2 modules
FPGA configures itself from an attached industry-standard (third-party) SPI serial Flash PROM. The FPGA supplies the CCLK output clock from its internal oscillator and drives the clock input of the attached SPI Flash PROM.
When the FPGA mode pins are set for JTAG mode (M[2:0] = <1:0:1> in TE0320 and TE0300 module), the FPGA waits to be configured via the JTAG port after a power-on event or after PROG_B is pulsed Low. Selecting the JTAG mode simply disables the other configuration modes. No other pins are required as part of the configuration interface.
While there is no specific mode for JTAG (in TE0630 module), the JTAG interface is available as a configuration interface any time the device is powered.
When using Slave Parallel mode configuration, an external host, such as a microprocessor or microcontroller (the USB FX2 microcontroller for the TE USB FX2 module), writes byte-wide configuration data (16 bit are not available in TE USB FX2 modules) into the FPGA, using a typical peripheral interface. See "Slave Parallel (SelectMAP) Mode" of ug332 or "SelectMAP Configuration Interface" of ug380.
In Slave Serial mode, an external host such as a microprocessor or microcontroller (the USB FX2 microcontroller for the TE USB FX2 module) writes serial configuration data into the FPGA, using a synchronous serial interface.
See also
.Spartan-3E (TE0300 module) | FPGA image (bitstream) could be retrieved from | ||||||
---|---|---|---|---|---|---|---|
M[2:0] | Configuration Mode | Bus Width | CCLK Direction (FPGA based) | TE0300's SPI Flash memory | TE0300's Jtag connection | TE0300's USB connection | B2B connection |
WITHOUT HW modification (desoldering/resoldering) of M10, V11 connection with 3.3V and Gnd, it is only possible to use two type of configurations. | |||||||
<0:0:1> | Master SPI Mode | 1 | Output | ||||
<1:0:1> | JTAG Mode | 1 | Input (TCK) | (1) | |||
WITH HW modification (desoldering/resoldering) of M10, V11 connection with 3.3V and Gnd, it is also possible to use these two type of configurations. | |||||||
<1:1:0> | Slave Parallel (Select MAP) Mode | 8 | Input | (2) | |||
<1:1:1> | Slave Serial Mode | 1 | Input | (2) |
LEGEND:
M[2:0] | Spartan-3E (TE0300 module) | Component required (not mounted on TE0300 module) |
---|---|---|
<0:0:0> | Master Serial (Platform Flash) Mode | Xilinx Platform Flash |
<0:1:0> | BPI Up | third-party BPI Flash |
<0:1:1> | BPI Down | third-party BPI Flash |
Spartan-3A DSP (TE0320 module) | Source of FPGA image (bitstream). It could be retrieved from | ||||||
---|---|---|---|---|---|---|---|
M[2:0] | Configuration Mode | Bus Width | CCLK Direction (FPGA based) | TE0320's SPI Flash memory | TE0320's Jtag connection | TE0320's USB connection | B2B connection |
<0:0:1> | Master SPI Mode | 1 | Output | ||||
<1:0:1> | JTAG Mode | 1 | Input (TCK) | (1) | |||
<1:1:0> | Slave Parallel (Select MAP) Mode | 8 | Input | (2) | |||
<1:1:1> | Slave Serial Mode | 1 | Input | (2) |
LEGEND:
M[2:0] | Spartan-3A DSP (TE0320 module) | Component required (not mounted on TE0320 module) |
---|---|---|
<0:0:0> | Master Serial (Platform Flash) Mode | Xilinx Platform Flash |
<0:1:0> | BPI Up | third-party BPI Flash |
All mode selection pins are hardwired (they do not exist as switches).
Spartan-6 (TE0630 module) | Source of FPGA image (bitstream). It could be retrieved from | ||||||
---|---|---|---|---|---|---|---|
M[1:0] | Configuration Mode | Bus Width | CCLK Direction (FPGA based) | TE0630's SPI Flash memory | TE0630's Jtag connection | TE0630's USB connection | TE0630's B2B connection |
WITHOUT HW modification (desoldering/resoldering) of U15, Y18 connection with 3.3V and Gnd, it is only possible to use two type of configurations. | |||||||
<0:1> | Master Serial/SPI | 1,2 or 4 | Output | ||||
<x:x> (1) | JTAG Mode | 1 | Input (TCK) | (2) | |||
WITH HW modification (desoldering/resoldering) of U15, Y18 connection with 3.3V and Gnd, it is only possible to use two type of configurations. | |||||||
<1:0> | Slave Parallel (SelectMap) Mode | 8 (3) | Input | (4) | |||
<1:1> | Slave Serial Mode | 1 | Input | (4) |
LEGEND:
(1) Spartan-6 devices also have a dedicated four-wire JTAG (IEEE Std 1149.1) port that is always available to the FPGA regardless of the mode pin settings.
(2)
(3) 16 bit inteface is theoretically possble but is not supported in the TE0630 module.
(4)
M[1:0] | Spartan-6 (TE0630 module) | Component required (not mounted on TE0630 module) |
---|---|---|
<0:0> | Master SelectMAP/BPI | third-party BPI Flash |