TEB0729 TRM

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Overview

The Trenz Electronic TEB0729 is a Carrier Board designed especially for the TE0729 Zynq-7000 SoM. The board exposes the module's B2B connector pins to accessible connectors and provides on-board peripheral components to test and evaluate TE Zynq-7000 SoMs and for developing purposes..

The Carrier Board provides soldering-pads for VG96 connectors as place-holders to get access to the PL-IO-banks and other functional units of the mounted SoM.

Key Features

• Barrel jack for 5V power supply
• 2x RJ45 10/100-BaseT Ethernet MagJack with 2 integrated LEDs
• 1x RJ45 Gigabit Ethernet MagJack with 2 integrated LEDs.
• 2x Configuration EEPROM's, connected to SoM's I²C interface
  
• XMOD compatible header to connect the TE0790 USB2.0 adapter board
• JTAG and UART interface over XMOD header
  
• MicroSD Card socket, can be used to boot system
• USB2.0 socket (Option: USB Type A or Micro USB2.0 B)
• 4-bit DIP switch for SoM configuration (SoM's JTAG access and Bootmode)
• VG96 connector soldering-pads J8 for access to SoM's PL-IO-bank-pins, usable as LVDS-pairs
• VG96 connector soldering-pads J9 for access to further interfaces and IO's of the SoM
• 1 x user LED (red) routed to SoM
  
• 1 x user push-button routed to SoM (Reset function at standard configuration)
• Pin headers to set PL-IO-bank's VCCIO with jumper

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TEB0729-02 block diagram.

Main Components

Figure 2: TEB0729-02 main components.

1. 5V barrel jack, J12
2. RJ-45 Gigabit Ethernet MegJack, J3
3. RJ-45 10/100-BaseT Ethernet MegJack, J4
4. RJ-45 10/100-BaseT Ethernet MegJack, J5
5. VG96 connector placeholder, J9
6. XMOD (TE0790) header, JB3
7. 2-pin header for VBAT-IN supply-voltage, J2
8. 2x6 pin header for setting VCCIO_33, J6
9. 2x6 pin header for setting VCCIO_13, J7
10. MicroSD Card socket, J1
11. Red LED, D1
12. Push Button, S1
13. Micro USB2.0 B Receptacle (optional USB2.0 Type A socket)
14. VG96 connector placeholder, J8
15. B2B Connector, JB1
16. B2B Connector, JB2
17. 4-bit DIP-switch, S2

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

Signals, Interfaces and Pins

B2B Connector

The TEB0729 Carrier Board's Board-to-Board Connectors (B2B) have the same pin-assignment as the mounted Zynq SoM. By this connectors, the MIO- and PL-IO-bank's pins and further interfaces of the Zynq SoM can be accessed. A large quantity of these I/O's are also usable as LVDS-pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.

Following table gives a summary of the available I/O's, interfaces and LVDS-pairs of the B2B connectors JB1 and JB2:

Table 2: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

VG96 Connector

The TEB0729 Carrier Board has soldering pads provides as place-holders to mount VG96 connectors J8 and J9 to get access the PL-IO-bank's pins and further interfaces of the Zynq SoM. With mounted VG96 connectors, SoM's IO's are available to the user, a large quantity of these I/O's are also usable as  LVDS-pairs.

On the VG96 connector J9 are signals assigned to control the SoM and the interfaces of the SoM's Zynq chip and of its on-module peripherals:

Following table gives a summary of the pin-assignment, available interfaces and functional IO's of the VG96 connectors J8 and J9:

Table 3: General overview of PL I/O signals, SoM's interfaces and control signals  connected to the VG96 connectors.

HW-modification Concerning Reset-Signals

¹⁾ The pins with the schematic net names 'NRST_IN' (JB2-89) and 'NRST_OUT' (JB2-91) are swapped as part of a HW-modification to rework the Reset-signals of the Carrier-Board in conjunction with the TE0729 SoM.

Refer to the SC CPLD documentation, section "Watchdog" to get further detailed information about the Reset-functionality of the Carrier Board and SoM before and after the HW-modification and the required SC CPLD firmware revision of the TE0729 SoM for each version of the SoM.

JTAG Interface

JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JB3. With the TE0790 XMOD USB2.0 to JTAG adapter, the Zynq chip on the mounted SoM can be programed via USB2.0 interface.

Table 4: JTAG interface signals.

UART Interface

UART interface is available on B2B connector JB2. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

Table 5: UART interface signals.

I²C Interface

Two I²C interfaces are provided on B2B connector JB2. I²C0 interface is connected to the Configuration EEPROMs U1 and U2 and is dedicated to these on-board peripherals. Interface I²C1 is routed to the VG96 connector J9 and is available to the user for general purposes:

Table 6: I²C interface signals.

SD IO Interface

The SD IO interface of the SoM's Zynq chip (MIO-bank) is routed to the on-board MicroSD Card socket J1. By this interface, the Zynq chip can be booted from an inserted MicroSD Card:

Table 7: SD IO interface signals.

USB2.0 Interface

The TEB0729 Carrier Board is equipped with a Micro USB2.0 B (receptacle) socket J11 with board-revision TEB0729-02B, USB2.0 Type A socket is fitted on board-revision TEB0729-02A.

The differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the USB2.0 transceiver of the mounted SoM. The USB2.0 connector can be used for Device mode, OTG Mode or Host Modes. For USB Host mode, the Carrier Board is additionally equipped with a power distribution switch U3 to provide the USB2.0 interface with the USB supply voltage USB-VBUS with nominal value of 5V. OTG mode is not available with USB2.0 Type A socket.

Following table gives an overview of the USB2.0 interface signals:

Table 8: USB2.0 interface signals and connections.

Gigabit Ethernet Interface

The TEB0729 Carrier Board is fitted with one RJ-45 Gigabit Ethernet Magnetic jack J3. The MegJack has two integrated LEDs (both green), its signals are routed as MDI (Media Dependent Interface) to the B2B connector JB2, where they can be accessed by the GbE PHY transceiver of the mounted SoM:

Table 9: GbE interface signals and connections.

For the same GbE transceiver PHY on the mounted SoM, on the Carrier Board is also SGMII (Serial Gigabit Media Independent Interface) available. The SGMII pins are available on VG96 connector J9:

Table 10: GbE SGMII signals and connections.

10/100-BaseT Ethernet Interface

The TEB0729 Carrier Board is also fitted with two additional RJ-45 MegJacks providing 10/100-BaseT Ethernet interfaces. This interfaces are routed to the B2B connector JB2

Table 11: 10/100-BaseT Ethernet interfaces signals and connections.

XMOD FTDI JTAG-Adapter Header

The JTAG interface of the mounted SoM can be accessed via header JB3, which has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment. So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB interface. The TE0790 board provides also an UART interface to the Zynq SoM which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted. The adapter-board offers also two GPIO's, one with an indication LED (pin JB3-9 (E)) and another one with a low-active push button (pin JB3-11 (G)).

Following table describes the signals and interfaces of the XMOD header JB3:

Table 12: XMOD header signals and connections.  ²⁾ Swapped at HW-Modification with signal 'NRST_OUT' in board-revision 2

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the Carrier Board. Set the DIP-switch with the setting:

Table 13: XMOD adapter board DIP-switch positions for voltage configuration.

On-board Peripherals

Configuration EEPROM

The TEB0729 Carrier Board is equipped with two Configuration EEPROMs U1 and U2 from Microchip.

• U1: Microchip 24LC128: 128 KBit memory density (8 pages a 16 KBit), 400 KHz max. clock frequency
  • I²C-Address: 1010 101

• U2: Microchip 24AA025E48T: 2 KBit memory density (2 block of 128 x 8-bit words), 400 KHz max. clock frequency
  • I²C-Address: 1010 011

The Configuration EEPROMs are connected to the I²C0 interface of the Zynq's MIO-bank via B2B connector JB2.

4-bit DIP-switch

Table below describes DIP-switch S2 settings for configuration of the mounted SoM:

Table 14: DIP-Switch S2 SoM configuration settings

Table 15: Bootmode configuration via DIP-switch S2

VCCIO Setting Jumper

The Carrier Board VCCIO for the PL IO-banks of the mounted SoM are selectable by the jumpers J6 and J7.

Following table describes how to configure the VCCIO of the SoM's banks with jumpers:

Table 16: VCCIO jumper settings.

RTC Buffer Voltage Supply Header

The buffer voltage of the SoM's RTC can be supplied through the header J2. Refer to the SoM's TRM for recommended voltage range and absolute maximum ratings.

Push Button

The Carrier Board's push button S1 is connected to the 'NRST_IN' signal, the function of the button is to trigger a reset of the mounted SoM by driving the reset-signal 'NRST_IN' to ground.

On-board LEDs

Table 17: On-board LEDs.

Power and Power-On Sequence

Power Consumption

The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq chip.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 18: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

Power Distribution Dependencies

The Carrier Board needs one single power supply voltage with a nominal value of 5V. Following diagram shows the distribution of the input voltage '5VIN' to the on-board components on the mounted SoM:

Figure 3: Board power distribution diagram.

Power Rails

Table 19: Power pin description of B2B Module Connector.

Table 20: Power Pin description of VCCIO selection jumper pin header.

Table 21: Main Power jack and pins description.

Table 22: Power pin description of peripheral connector.

Table 23: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

The TE0729 module has two 120-pin double-row REF-189019-02 connectors on the bottom side which are compatible with Samtec BSE-060-01-L-D-A connectors. Mating connectors on the baseboard are REF-189019-01, which are compatible with Samtec BTE-060-01-L-D-A connectors.

Table 24: B2B Connectors.

Variants Currently In Production

Table 25: Module variants.

Technical Specifications

Absolute Maximum Ratings

Table 26: Module absolute maximum ratings.

Recommended Operating Conditions

Table 27: Module recommended operating conditions.

Operating Temperature Ranges

Industrial grade: -40°C to +85°C.

The TEB0729 Carrier Board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted SoM, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

• Board size: 107.70 mm × 100 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8 mm.

• PCB thickness: ca. 1.65mm.

• Highest part on the PCB is the Ethernet RJ-45 jack, which has an approximately 17 mm overall height. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Figure 4: Board physical dimensions drawing.

Revision History

Hardware Revision History

Table 28: Module hardware revision history.

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Figure 5: Module hardware revision number.

Document Change History

Date	Revision	Contributors	Description
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]		Ali Naseri	initial document

Table 29: Document change history.

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