TEBF0808 TRM

Overview

The Trenz Electronic TEBF0808 carrier board is a baseboard for the Xilinx Zynq Ultrascale+ MPSoC modules TE0808 and TE0803, which exposes the module's B2B connector pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ SoMs and for developing purposes. The carrier board has a Mini-ITX form factor making it capable to be fitted into a PC enclosure. On the PC enclosure's rear and front panel, MGT interfaces and connectors are accessible, for the front panel elements there also Intel-PC compatible headers available. 

Key Features

• Mini-ITX form factor, PC enclosure compatible
• ATX-24 power supply connector
• Optional 12V standard power plug
• Headers
  • Intel 10-pin HDA Audio
  • Intel 9-pin Power-/Reset-Button, Power-/HD-LED
  • PC-BEEPER
• On-board Power- / Reset-Switches
• 2x Configuration 4-bit DIP-switches
• 2x Optional 4-wire PWM fan connectors
• PCIe Slot - one PCIe lane (16 lane connector)
• CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
• 4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x  Microchip 24AA025E48T-I/OT)
• Dual SFP+ Connector (2x1 Cage)
• 1x DisplayPort (single lane)
• 1x SATA Connector
• 2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
• 1x USB3.0 on-board connector with two ports
• FMC HPC Slot (FMC_VADJ max. VCCIO)
• FMC Fan
• Gigabit Ethernet RGMII PHY with RJ45 MegJack
• All carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
• Quad programmable PLL clock generator SI5338A
• 2x SMA coaxial connectors for clock signals
• MicroSD- / MMC-Card Socket (bootable)
• 32 Gbit (4 GByte) on-board eMMC flash (8 banks a 4 Gbit)
• 2x System Controller CPLDs Lattice MachXO2 1200 HC
• 1x Samtec FireFly (4 GT lanes bidirectional)
• 1x Samtec FireFly connector for reverse loopback
• 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLDs
• 20-pin ARM JTAG Connector (PS JTAG0)
• 3x PMOD connector (GPIO's and I²C interface to SC CPLDs and MPSoC module)
• On-board DC-DC PowerSoCs

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TEBF0808-04 Block Diagram

Main Components

Figure 2: TEBF0808-04 Carrier Board

1. PMOD connector, P2
2. MicroSD Card socket (on bottom side), J16
3. DisplayPort connector, J13
4. USB3.0 A 2x , RJ45 1x (stacked), J7
5. SFP+ 2x1 cage, J14
6. PCIe x16 connector (one PCIe lane connected), J11
7. FMC HPC connector, J5
8. FMC-Fan connector 5V, J19
9. USB3.0 connector, J8
10. PC-BEEPER 4-pin header, J23
11. SMA coaxial connector (SI5338A clock output), J32
12. SMA coaxial connector (clock input to MPSoC module), J33
13. MMC Card socket, J27
14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
18. CAN bus 6-pin header, J29
19. CAN bus 10-pin connector, J24
20. ARM JTAG  20-pin connector, J30
21. ATX-24 power supply connector, J20
22. 4-Wire PWM fan connector, J35
23. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to MPSoC module, J12
24. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to System Controller CPLDs, J28
25. Power Jack 2.1mm 12V, J25
26. 4-bit DIP-switch, S5
27. Power Button, S1
28. Samtec FireFly connector  for reverse loopback, J21/J22
29. Samtec FireFly connector (4 GT lanes bidirectional), J6/J15
30. SATA header, J31
31. 4-Wire PWM fan connector, J26
32. I²C interface of programmable on-module PLL (10-pin header), J17
33. Reset Button, S2
34. INTEL HDA 9-pin header, J9
35. Intel front panel (PWR-/RST-Button, HD-/PWR-LED) 9-pin header, J10
36. Samtec FireFly connector J6/J15 I²C interface (3-pin header), J34
37. 4-bit DIP-switch, S4
38. PMOD connector, P3
39. PMOD connector, P1
40. Battery Holder CR1220, B1

Initial Delivery State

Table 1: Initial Delivery State of the flash memories

Signals, Interfaces and Pins

FMC HPC Connector

The FMC (FPGA Mezzanine Card) connector J5 with high pin count (HPC) provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.

The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.

Figure 3: FMC HPC Connector

Table 2: FMC connector pin-outs of available logic banks of the MPSoC

The MGT-banks have also clock input-pins which are exposed to the FMC connector. Following MGT-lanes are available on the FMC connectors J5:

Table 3: FMC connector pin-outs of available MGT lanes of the MPSoC

The FMC connector provides pins for reference clock output to the Mezzanine module and clock input to PL banks of the MPSoC:

Table 4: FMC connector pin-outs for reference clock output

The FMC connector provides further interfaces like JTAG and I²C interfaces:

Table 5: FMC connector pin-outs of available interfaces to the System Controller CPLD

Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:

Table 6:  Available VCCIO voltages on FMC connector

MIO Bank Interfaces

The TEBF0808 carrier board provides several interfaces, which are configured on the MIO banks 500 .. 503 of the Zynq Ultrascale+ MPSoC.

Following table contains the assignment of the MIO pins to the configured interfaces:

Table 7:  MIO Assignment

Following interfaces are provided by the MIO bank of the Zynq Ultrascale+ MPSoC:

• 4x USB3.0 Superspeed ports (downward compatible to USB2.0 Highspeed)
• SDIO port with muxed MikroSD and MMC Card socket
• Gigabit Ethernet interface connected per RGMII
• eMMC interface
• Master I²C interface to on-board peripherals

The block-diagram below visualizes the interfaces of the MIO bank at the Zynq Ultrascale+ MPSoC and their associated on-board peripherals.

Figure 4: TEBF0808 MIO Interfaces

PS GT Bank 505 Interfaces

The PS GT Bank 505 provides beside the USB3.0 Lane also following interfaces:

• SATA (PS GT bank 505, MGT2 Lane)
• DisplayPort (PS GT bank 505, MGT3 Lane, only TX-pair routed)
• PCI Express (PS GT bank 505, MGT0 Lane)
  
  

Table 8:  PS GT Lane Assignment

Following block diagram shows the wiring of the MGT Lanes of the PS GT bank 505 to the particular high speed data interfaces:

Figure 5: TEBF0808 PS GT Bank 505 Interface

MGT Interfaces SFP+ and FireFly

The TEBF0808 carrier board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) and Samtec "FireFly". Each of this connectors are capable of data transmission rates up  to 10 Gbit/s.

Table 9:  MGT Lane Assignment

Following block diagram show the wiring of the MGT lanes to the particular interface connectors:

Figure 6: TEBF0808 MGT Interfaces

As shown on the block diagram, the FireFly connector pair J21, J22 provides four reversed looped back MGT lanes. To test any of the on-board MGT lanes or of an extern device, 4 RX/TX differential pairs are bridged on the connector, hence the transmitted data on these MGT lanes flows back to their sources in a loop-back circuit without intentional processing or modification.

CAN FD Interface and PMOD Connectors

On the carrier board there is a CAN FD (CAN with Flexible Data-Rate) interface available which is accessible on the CAN headers J24 (10-pin IDC connector) or J29 (6-pin header), which are connected to the CAN FD transceiver U30.

Additionally the carrier board provides PMOD connectors with GPIO and I²C interface:

Table 10:  PMOD Pin Assignment

Figure 7: TEBF0808 CAN Interfaces, PMOD

Intel-PC Compatible Headers and FAN Connectors

The TEBF0808 carrier board provides with its Mini-ITX form factor the possibility to encase the boa rd in a PC Enclosure. For this purpose, the board is equipped with several Intel-PC compatible headers to connect them to the PC Enclosure.

Headers are available for following PC front panel elements

• Reset Button
• Power Button
• Power LED
• Hard Disc (HD) LED
• Intel High Definition Audio (HDA) Jacks

Following table gives an overview about the particular headers and a description about their functionalities:

Table 11: PC compatible Headers

Figure 8: TEBF0808 PC Compatible Headers

JTAG Interface

The TEBF0808 carrier board provides several JTAG interfaces to program both the System Controller CPLDs and the Zynq Ultrascale+ MPSoC.

Therefore, the board is equipped with two JTAG/UART headers, which have 'XMOD FTDI JTAG Adapter'-compatible pin-assignment. So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM and the System Controller CPLDs can be programmed via USB interface.

The System Controller CPLDs will be programmed by the XMOD-Header J28 in a cascaded JTAG chain as visualized in Figure 8. To program the System Controller CPLDs, the JTAG interface of these devices have to be activated by DIP-switch S4-3.
The 4 GPIO/UART pins (XMOD1_A/B/E/G) of the XMOD-Header J28 are routed to the System Controller CPLD U17.

XMOD-Header J12 is designated to program the Zynq Ultrascale+ MPSoC via USB interface, the 4 GPIO/UART pins (XMOD2_A/B/E/G) of this header are routed to the System Controller CPLD U39.

Figure 9: TEBF0808 JTAG interfaces

Further JTAG interfaces of the TEBF0808 carrier board are the ARM JTAG 20-pin IDC connector J30 and on the FMC Connector J5. This JTAG interfaces are connected to the System Controller CPLD U17, hence the logical processing and forwarding of the JTAG signals depend on the SC CPLD firmware. The documentation of the firmware of the SC CPLD U17 contains detailed information on this matter.

On-board Peripherals

System Controller CPDLs

The TEBF0808 is equipped with two System Controller CPLDs - Lattice Semiconductor LCMXO2-1200HC (MachXO2 Product Family) - with the schematic designators U17 and U39.

The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic of the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

Both Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank pins and I²C interface. The CPLDs are connected with each other through the IO pins SC_IO0 ... SC_IO8.

The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U17 and SC CPLD U39 contains detailed information on this matter.

Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS (MIO), PL bank pins and I²C interface.

Figure 10: TEBF0808 System Controller CPLDs

Programmable PLL Clock Generator

The TEBF0808 Carrier Board is equipped with a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U35). It's output frequencies can be programmed by using the I²C bus with address 0x70.

A 25 MHz (U7) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.

Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected through I²C switch U16 between the Zynq module (master) and reference clock signal generator (slave).

Table 12: Pin description of PLL clock generator Si5338A

Figure 11: Clocking Configuration of TE0808 SoM on TEBF0808 Carrier Board

Si5338 OTP can only be programmed two times, as different user configurations may required different setup, TEBF0808 is normally shipped with blank OTP.
For more information Si5338 at SiLabs.

Oscillators

The TEBF0808 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:

Table 13: Reference clock signal oscillators

High-speed USB ULPI PHY

USB PHY (U9) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U10).

Table 14: USB PHY interface connections

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U12) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U13). The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U17, pin 70.

Table 15: Ethernet PHY interface connections

8-Channel I²C Switches

All on-board peripherals's interfaces and on-module peripherals with exposed I²C interface to B2B connectors are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.

For this purpose, the TEBF0808 carrier board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channels.

Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches. 

The I²C bus works internally on-module with reference voltage 1.8V, it is connected to the PS I²C interface via PS MIO bank 501, pins MIO38 and MIO39, configured as master.

Table 16: MIO-pin assignment of the module's I²C interface

I²C addresses for on-board slave devices are listed in the table below:

Table 17:  On-board peripherals' I²C-interfaces device slave addresses

There are further I²C interfaces connected to the 8-channel I²C switches U16 and U27, which are provided by connectors with I²C interface. The I²C slave addresses depend on the devices, which are attached to this connectors:

Table 18:  On-board connectors' I²C-interfaces overview

Configuration EEPROMs

The TEBF0808 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:

Table 19:  On-board configuration EEPROMs overview

4-port USB3.0 Hub

On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub controller U4. The pin-strap configuration option of the USB3.0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16.

On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank 505 to establish the USB3.0 data lane. For the USB2.0 interface, the controller is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank 501.

The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.

CAN FD Transceiver

On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.

The transceiver is connected to System Controller CPLD U17, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD U17.

eMMC Memory

The TEBF0808 carrier board is equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.

24-bit Audio Codec

For high resolution digital audio signal processing, the TEBF0808 carrier board is equipped with the Analog Devices 24-bit Audio Codec chip ADAU1761 with the schematic designator U3. The Audio Codec chip is connected to the Intel High Defintion Audio (Intel HDA) compatible 9-pin header J9 with single-ended signaling for analog stereo audio signal input and output. It supports also MIC / Jack detect. Its I²C control interface is accessible by the Zynq Ultrascale+ MPSoC through I²C switch U27.

The 24-bit Audio Codec provides numerous features and is also fully programmable with its dedicated graphical tool from the manufacturer. Refer to the data sheet of this chip for more detail information and specifications.

SDIO Port Expander

Due to the different signaling voltage levels of the MicroSD and MMC Card interfaces (3.3V) and the PS MIO bank of the Zynq Ultrascale+ MPSoC (1.8V), there is voltage-translation necessary, which is fullfilled by the SDIO port expander Texas Instruments TXS02612, U15. This IC also muxes the MikroSD and the MMC Card sockets to the SDIO port of the MPSoC, which is controlled by the signal 'SEL_SD' of the System Controller CPLD U39. The SC CPLD U39 also controls the load switches to enable the card sockets J16 and J27 and to report the card detect signal both of the sockets to the MPSoC (see schematic).

DIP-Switches

There are two 4 bit DIP Switches on the TEBF0808 carrier board to configure options and set parameters. The table below describes the functionalities of the particular switches:

Table 20: DIP-switch S4 functionality description

DIP-switch S5 located close to PWR push-button is connected to the two System Controller CPLDs, its functionalities depend on the current firmware of the CPLDs.

The switches of this DIP-switch have to be set in bit-patterns to set a parameter like boot mode or FMC_VADJ value:

Table 21: DIP-switch S4 functionality description

On-board LEDs

The TEBF0808 carrier board is equipped with several LED to signal current states and activities. The functionality of the LEDs D4 ... D7 depends on the current firmware of the SC CPLDs U17 and U39.

Table 22: On-board LEDs functionality description

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Management

The TEBF0808 carrier board manages both the power-on sequence of the mounted TE0808 SoM and the on-board DC-DC converters via System Controller CPLD U39.

The power-on sequence of the TE0808 SoM is managed by utilizing the SoM's DC-DC converter control signals ('Enable', 'Power-Good'), so the DC-DC converters of the SoM dedicated to the particular Power Domains of the Zynq Ultrascale+ MPSoC will be powerer-up in a specific sequence to meet the recommended criteria to power up the Xilinx Zynq Ultrascale+ MPSoC properly.

Figure 12: TEBF0808 Power-Management

Adjustable PL Bank VCCO Voltage FMC_VADJ

The carrier board VCCO voltage 'FMC_VADJ' supplying the PL IO-banks of the MPSoC (bank 64, 65, 66, 48) is provided by DC-DC converter U8 and selectable by the pins 'FMC_VID0' ... 'FMC_VID2' of the System Controller CPLD U17.

Table 3: Bit patterns for fixed values of the FMC_VADJ voltage

Note: These pins of the DC-DC converter U8 are hard-wired to initialiy fix the voltage to 1.8V (see schematic).

Power Distribution Dependencies

All on-board voltages of the TEBF0808 are generated out of the extern applied 12V power supply.

There are following dependencies how the initial 12V power supply is distributed to the on-board DC-DC converters, which power up further DCDC converters and the particular on-board voltages:

Figure 13: Power Distribution Diagram

Power-On Sequence Diagram

The power-on sequence of the on-board DC-DC converters depens on the current firmware of the System Controller CPLD U17.

Following diagram visualizes the connection of the DC-DC converter control signals ('Enable', 'Power-Good') with System Controller CPLD U17, which enables the particular on-board voltages.

Figure 14: Power-On Sequence Utilizing DCDC Converter Control Signals

Core voltages and main supply voltages of the Zynq Ultrascale+ MPSoC have to reach stable state and the "Power Good"-signals of the SoM have to be asserted before other voltages like bank's I/O voltages (VCCOx) can be powered up.

It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are logically high, meaning that all on-module voltages have become stable and module is properly powered up.

B2B connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 170 mm × 170 mm.  Please download the assembly diagram for exact numbers

• Mating height with standard connectors: 5 mm

• PCB thickness: 1.844 mm ± 10%

• Highest part on PCB: approx. 32 mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

Revision History

Hardware Revision History

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Document Change History

Date	Revision	Contributors	Description
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy241.$Proxy3496#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]		Ali Naseri	Initial document

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