TEF1001 TRM

Download PDF version of this document.

Table of Contents

Overview

The Trenz Electronic TEF1001 FPGA board is a PCI Express form factor card integrating the Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC. The FPGA-board is designed for high system resources and intended for use in applications with high demands on system performance and throughput. To extent the board with standard DDR3 SDRAM memory module, there is a 204-pin SODIMM socket with 64bit databus width on the board present. Highspeed data transmission is enabled by the 4 lane PCIe Gen 2 interface.

The board offers a HPC (High Pin Count) ANSI/VITA 57.1 compatible FMC interface connector for standard FPGA Mezzanine cards and modules. Other interface connectors found on-board include JTAG for accessing FPGA and on-board System Controller CPLD.

The TEF1001 FPGA board is intended to be used as add-on card in a PCIe 2.0 or higher capable host system to meet the power supply requirements.

Key Features

Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC
Large number of configurable I/Os are provided via HPC FMC connector
- 4 GTX high-performance transceiver
- 2x MGT transceiver clock inputs
- 160 FPGA I/O's (80 LVDS pairs)
Si5338A programmable quad PLL clock generator for GTX transceiver clocks
On-board high-efficiency switch-mode DC-DC converters
Lattice MachXO2 LCMXO2-1200HC System Controller CPLD
10x User LEDs
PCI Express x8 connector with 4 lane PCIe Gen 2 interface
ANSI Vita 57.1 FMC High Pin Count (HPC) connector
DDR3 SODIMM SDRAM socket with 64bit databus width
256 Mbit (32 MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
- FPGA
- JTAG port (SPI indirect, bus width x4)
FPGA configuration through:
- JTAG connector
- Quad SPI Flash memory
Clocking
- - Si5338 - 4 output PLLs, GT and PL clocks
- - 200 MHz oscillator for DDR3 bank
System management and power sequencing
AES bit-stream encryption
eFUSE bit-stream encryption

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TEF1001-02 block diagram

Main Components

Figure 2: TEF1001-02 main components

Xilinx Kintex XC7K-2FBG676I FPGA SoC, U6
ANSI/VITA 57.1 compliant FMC HPC connector, J2
Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM), M1
PCIe x8 connector, J1
DDR3 SODIMM 204-pin socket, U2
6-pin 12V power connector, J5
Step-down DC-DC converter @1.5V and @4V (LT LTM4676A), U3
Step-down DC-DC converter @1.0V (LT LTM4676A), U4
256 Mbit Quad SPI Flash Memory (Micron N25Q256A), U12
10x Green user LEDs connected to FPGA, D1 ... D10
4-wire PWM fan connector, J4
User button, S2
FPGA JTAG connector, J9
4bit DIP switch, S1
I²C header for LTM4676A DC-DC converter, J10
System Controller CPLD JTAG header, J8
1x Green LED connected to SC CPLD, D11
2-pin 5V FAN header, J6
System Controller CPLD (Lattice Semiconductor LCMXO2-1200HC), U5
6A PowerSoC DC-DC converter @FMC_VADJ (Altera EN5365QI), U7
4A PowerSoC DC-DC converter @3.3V (3V3FMC) (Altera EN6347QI), U15
LDO converter @1.2V (MGTAVTT_FPGA) (TI TPS74401RGW), U17
LDO converter @1.0V (MGTAVCC_FPGA) (TI TPS74401RGW), U18
4A PowerSoC DC-DC converter @1.8V (Altera EN6347QI), U7

Initial Delivery State

Storage device name	Content	Notes
Si5338A OTP Area	not programmed	-
SPI Flash OTP Area	Empty, not programmed	Except serial number programmed by flash vendor
SPI Flash Quad Enable bit	Programmed	-
SPI Flash main array	demo design	-
HyperFlash Memory	not programmed	-
eFUSE USER	Not programmed	-
eFUSE Security	Not programmed	-

Table 1: Initial delivery state of programmable devices on the module

Boot Process

By default the configuration mode pins M[2:0] of the FPGA are set to QSPI mode (Master SPI), hence the FPGA is configured from QSPI Flash memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI Flash memory.

Signals, Interfaces and Pins

FMC HPC Connector I/Os

I/O signals connected to the SoCs I/O bank and FMC connector J2:

FPGA Bank	Type	I/O Signal Count	Bank VCCO Voltage	Notes
12	HR	48 IO's, 24 LVDS pairs	FMC_VADJ	Bank voltage FMC_VADJ is supplied by DC-DC converter U7
13	HR	34 IO's, 17 LVDS pairs	FMC_VADJ
15	HR	34 IO's, 17 LVDS pairs	FMC_VADJ
16	HR	44 IO's, 22 LVDS pairs	VIO_B_FMC	Bank voltage VIO_B_FMC is supplied by FMC connector J2

Table 2: General overview of FPGA's PL I/O signals connected to the FMC connector

For detailed information about the pin out, please refer to the Pin-out Tables.

PCI Express Interface

The TEF1001 FPGA board is a PCI Express card designed to fit into systems with PCI Express x8 slots and has a data transmission capability which meets PCIe Gen. 2. See next section for the overview of FPGA MGT lanes routed to the PCIe interface.

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. The MGT lanes are connected to the FMC connector and to the PCIe x8 connector. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, connector and FPGA pins connection:

Lane	Bank	Type	Signal Name	PCIe Connector Pin	FPGA Pin
0	115	GTX	PER3_P PER3_N PET3_P PET3_N	J1-A29 J1-A30 J1-B27 J1-B28	MGTXTXP0_115, P2 MGTXTXN0_115, P1 MGTXRXP0_115, R4 MGTXRXN0_115, R3
1	115	GTX	PER2_P PER2_N PET2_P PET2_N	J1-A25 J1-A26 J1-B23 J1-B24	MGTXTXP1_115, M2 MGTXTXN1_115, M1 MGTXRXP1_115, N4 MGTXRXN1_115, N3
2	115	GTX	PER1_P PER1_N PET1_P PET1_N	J1-A21 J1-A22 J1-B19 J1-B20	MGTXTXP2_115, K2 MGTXTXN2_115, K1 MGTXRXP2_115, L4 MGTXRXN2_115, L3
3	115	GTX	PER0_P PER0_N PET0_P PET0_N	J1-A16 J1-A17 J1-B14 J1-B15	MGTXTXP3_115, H2 MGTXTXN3_115, H1 MGTXRXP3_115, J4 MGTXRXN3_115, J3
Lane	Bank	Type	Signal Name	FMC Connector Pin	FPGA Pin
0	116	GTX	DP3_M2C_P DP3_M2C_N DP3_C2M_P DP3_C2M_N	J2-A10 J2-A11 J2-A30 J2-A31	MGTXRXP0_116, G4 MGTXRXN0_116, G3 MGTXTXP0_116, F2 MGTXTXN0_116, F1
1	116	GTX	DP2_M2C_P DP2_M2C_N DP2_C2M_P DP2_C2M_N	J2-A6 J2-A7 J2-A26 J2-A27	MGTXRXP1_116, E4 MGTXRXN1_116, E3 MGTXTXP1_116, D2 MGTXTXN1_116, D1
2	116	GTX	DP1_M2C_P DP1_M2C_N DP1_C2M_P DP1_C2M_N	J2-A2 J2-A3 J2-A22 J2-A23	MGTXRXP2_116, C4 MGTXRXN2_116, C3 MGTXTXP2_116, B2 MGTXTXN2_116, B1
3	116	GTX	DP0_M2C_P DP0_M2C_N DP0_C2M_P DP0_C2M_N	J2-C6 J2-C7 J2-C2 J2-C3	MGTXRXP3_116, B6 MGTXRXN3_116, B5 MGTXTXP3_116, A4 MGTXTXN3_116, A3

Table 3: FPGA to B2B connectors routed MGT lanes overview

Below are listed MGT banks reference clock sources:

Clock signal	Bank	Source	FPGA Pin	Notes
MGTCLK_5338_P	115	U13, CLK1A	MGTREFCLK0P_115, H6	Supplied by on-board Si5338A
MGTCLK_5338_N	115	U13, CLK1B	MGTREFCLK0N_115, H5	Supplied by on-board Si5338A
PCIE_CLK_P	115	J1-A13, REFCLK+	MGTREFCLK1P_115, K6	External clock from PCIe slot
PCIE_CLK_N	115	J1-A14, REFCLK-	MGTREFCLK1N_115, K6	External clock from PCIe slot
GBTCLK0_M2C_P	116	J2-D4	MGTREFCLK0P_116, D6	External clock from FMC connector
GBTCLK0_M2C_N	116	J2-D5	MGTREFCLK0N_116, D5	External clock from FMC connector
GBTCLK1_M2C_P	116	J2-B20	MGTREFCLK1P_116, F6	External clock from FMC connector
GBTCLK1_M2C_N	116	J2-B21	MGTREFCLK1N_116, F5	External clock from FMC connector

Table 4: MGT reference clock sources

JTAG Interface

There are three JTAG interfaces available on the TEF1001 board:

JTAG Interface	Signal Schematic Name	JTAG Connector Pin	Connected to
CPLD JTAG VCCIO: 3.3V Connector: J8	CPLD_JTAG_TMS	J8-1	SC CPLD, bank 0, pin 90
	CPLD_JTAG_TDI	J8-2	SC CPLD, bank 0, pin 94
	CPLD_JTAG_TDO	J8-3	SC CPLD, bank 0, pin 95
	CPLD_JTAG_TCK	J8-4	SC CPLD, bank 0, pin 91

FPGA JTAG VCCIO: 1.8V Connector: J9	FPGA_JTAG_TMS	J9-4	FPGA, bank 0, pin N9
	FPGA_JTAG_TCK	J9-6	FPGA, bank 0, pin M8
	FPGA_JTAG_TDO	J9-8	FPGA, bank 0, pin N8
	FPGA_JTAG_TDI	J9-10	FPGA, bank 0, pin L8

FMC JTAG VCCIO: 3.3V Connector: J2	FMC_TRST	J2-D34	SC CPLD, bank 2, pin 36
	FMC_TCK	J2-D29	SC CPLD, bank 2, pin 27
	FMC_TMS	J2-D33	SC CPLD, bank 2, pin 28
	FMC_TDI	J2-D30	SC CPLD, bank 2, pin 31
	FMC_TDO	J2-D31	SC CPLD, bank 2, pin 32

Table 5: JTAG interface signals

System Controller CPLD I/O Pins

Special purpose pins are connected to the System Controller CPLD and have following default configuration:

Pin Name	SC CPLD Direction	Function	Default Configuration
200MHZCLK_EN	out	control line	enables 200.0000MHz oscillator U1
BUTTON	in	user	Reset Button
CPLD_TDO	out	CPLD JTAG interface	-
CPLD_TDI	in
CPLD_TCK	in
CPLD_TMS	in
JTAG_EN	in
DDR3_SCL	in / out	I²C bus of DDR3 SODIMM socket	I²C connected to FPGA
DDR3_SDA	in / out	I²C bus of DDR3 SODIMM socket	I²C connected to FPGA
PLL_SCL	in / out	I²C bus of SI5338 quad clock PLL	I²C connected to FPGA
PLL_SDA	in / out	I²C bus of SI5338 quad clock PLL	I²C connected to FPGA
PCIE_RSTB	in	PCIe reset input	see current SC CPLD firmware
FEX_DIR / FEX0 ... FEX11	in / out	user GPIO	see current SC CPLD firmware
F1PWM	out	FPGA FAN control	see current SC CPLD firmware
F1SENSE	in	FPGA FAN control
FAN_FMC_EN	out	FMC FAN enable
FMC_PG_C2M	out	FMC signals and pins	see current SC CPLD firmware
FMC_PG_M2C	in
FMC_PRSNT_M2C_L	in
FMC_SCL	in / out	FMC I²C	I²C connected to FPGA
FMC_SDA	in / out	FMC I²C	I²C connected to FPGA
FMC_TCK		FMC JTAG	see current SC CPLD firmware
FMC_TDI
FMC_TDO
FMC_TMS
FMC_TRST
DONE	in	FPGA configuration signal	PL configuration completed
PROGRAM_B	out	FPGA configuration signal	PL configuration reset signal
LED1	out	LED status signal	see current CPLD firmware
FPGA_IIC_OE	in	FPGA I²C	I²C operation enable
FPGA_IIC_SCL	in / out		I²C clock line
FPGA_IIC_SDA	in / out		I²C data line
EN_1V8	out	Power control	enable signal DCDC U20 '1V8'
PG_1V8	in		power good signal DCDC U20 '1V8'
EN_3V3FMC	out		enable signal DCDC U15 'EN_3V3FMC'
PG_3V3	in		power good signal U15 'EN_3V3FMC'
EN_FMC_VADJ	out		enable signal DCDC U7 'FMC_VADJ'
PG_FMC_VADJ	in		power good DCDC U7 'FMC_VADJ'
VID0_FMC_VADJ, VID1_FMC_VADJ, VID2_FMC_VADJ	out		DCDC U7 power selection pin
VID0_FMC_VADJ_CTRL, VID1_FMC_VADJ_CTRL, VID2_FMC_VADJ_CTRL	in		Power selection of FMC_VADJ, forwarded to DCDC U7
LTM_1V5_RUN	out		enable signals of DCDC U3, U4 (LTM4676) see current CPLD firmware
LTM_4V_RUN	out
LTM_SCL	in / out	DCDC U3, U4 (LTM4676) I²C	I²C connected to FPGA
LTM_SDA	in / out	DCDC U3, U4 (LTM4676) I²C	I²C connected to FPGA
LTM1_ALERT	in	DCDC U3, U4 (LTM4676) control	see current CPLD firmware
LTM2_ALERT	in
LTM_1V_IO0	in / out
LTM_1V_IO1	in / out
LTM_1V5_4V_IO0	in / out
LTM_1V5_4V_IO1	in / out

Table 6: System Controller CPLD I/O pins

For detailed function of the pins and signals, the internal signal assignment and the implemented logic, look to the Wiki reference page of the module's SC CPLD or into its bitstream file.

Quad SPI Interface

Quad SPI interface is connected to the FPGA bank 14, QSPI clock is provided by FPGA config bank 0.

Signal Name	QSPI Flash Memory U12 Pin	FPGA Pin
FLASH_QSPI_CS	C2	RDWR_FCS_B_0, AH7
FLASH_QSPI_D0	D3	D00_MOSI_0, AA7
FLASH_QSPI_D1	D2	D01_DIN_0, Y7
FLASH_QSPI_D2	C4	D02_0, U7
FLASH_QSPI_D3	D4	D03_0, V7
FLASH_CFG_CCLK	B2	CCLK_0, V11

Table 7: Quad SPI interface signals and connections

I2C Interface

On-module I²C interface is routed from PL bank 65 I/O pins (PLL_SCL and PLL_SDA) to the I²C interface of Si5338 PLL quad clock generator U2, also two further pins of bank 65 can be used as external I²C interface of the modue:

I²C Interface

Schematic net names

Connected to

I²C Address

Notes

PL bank 65 I/O

'PLL_SCL', pin AB20

'PLL_SDA' pin AB19

Si5338 U2, pin 12

Si5338 U2, pin 19

0x70

default address

PL bank 65 I/O

'B65_SCL', pin Y19

'B65_SDA', pin AA19

B2B JM1, pin 95

B2B JM1, pin 93

-

Table 8: I²C slave device addresses

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

DDR3 SD-RAM SODIMM Socket

By default TE0841 module has two K4A8G165WB-BIRC DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 2 GBytes of on-module RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-module QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q512A11G1240E with 512-Mbit (64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

Programmable Clock Generator

There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

Si5338A Pin	Signal Name / Description	Connected to	Direction	Note
IN1	-	not connected	Input	not used
IN2	-	GND	Input	not used
IN3	Reference input clock	U3, pin 3	Input	25.000000 MHz oscillator, Si8208AI
IN4	-	GND	Input	I²C slave device address LSB.
IN5	-	not connected	Input	not used
IN6	-	GND	Input	not used
CLK0A	CLK1_P	U1, R23	Output	FPGA bank 45, default 100MHz*
CLK0B	CLK1_N	U1, P23	Output	FPGA bank 45, default 100MHz*
CLK1A	MGT_CLK1_N	U1, V5	Output	FPGA MGT bank 225 reference clock, default 125MHz*
CLK1B	MGT_CLK1_P	U1, V6	Output	FPGA MGT bank 225 reference clock, default 125MHz*
CLK2A	MGT_CLK3_N	U1, AB5	Output	FPGA MGT bank 224 reference clock, default 156,25MHz*
CLK2B	MGT_CLK3_P	U1, AB6	Output	FPGA MGT bank 224 reference clock, default 156,25MHz*
CLK3A	CLK0_P	U1, pin T24	Output	FPGA bank 45, default 156,25MHz*
CLK3B	CLK0_N	U1, pin T25	Output	FPGA bank 45, default 156,25MHz*

Table 9: Programmable quad PLL clock generator inputs and outputs, *PCB REV01 is not programmed

Oscillators

The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Clock Source

Frequency

Signal Name

Clock Destination

Notes

U3, SiT8208AI

25.000000 MHz

CLK

Si5338A PLL U2, pin 3 (IN3)

-

U11, DSC1123DL5

200.0000 MHz

CLK200M_P

FPGA bank 45, pin R25

Enable by FPGA bank 65, pin AF24

Signal: 'ENOSC'

CLK200M_N

FPGA bank 45, pin R26

Table 10: Reference clock signals

On-board LEDs

LED	Color	Connected to	Description and Notes
D1	Green	System Controller CPLD, bank 3	Exact function is defined by SC CPLD firmware.

Table 11: On-board LEDs

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Input	Typical Current
VIN	TBD*
3.3VIN	TBD*

Table 12: Typical power consumption

* TBD - To Be Determined soon with reference design setup.

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any FPGA's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

Figure 3: TEF1001-02 Power Distribution Diagram

Power-On Sequence

The TE0841 SoM meets the recommended criteria to power up the Xilinx FPGA properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the FPGA chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Figure 4: TEF1001-02 Power-On Sequence Diagram

Power Rails

Power Rail Name	B2B JM1 Pins	B2B JM2 Pins	Input/Output	Notes
VIN	1, 3, 5	2, 4, 6, 8	Input	Supply voltage
3.3VIN	13, 15	-	Input	Supply voltage
B64_VCO	9, 11	-	Input	HR (High Range) bank voltage
B66_VCO	-	1, 3	Input	HP (High Performance) bank voltage
B67_VCO	-	7, 9	Input	HP (High Performance) bank voltage
B68_VCO	-	5	Input	HP (High Performance) bank voltage
VBAT_IN	79	-	Input	RTC battery supply voltage
3.3V	-	10, 12, 91	Output	Module on-board 3.3V voltage level

Table 13: Module power rails

Bank Voltages

Bank	Schematic Name	Voltage	Voltage Range
0 (config)	PL_1.8V	1.8V	-
44 HP	DDR_1V2	1.2V	HP: 1.2V to 1.8V
45 HP	PL_1.8V	1.8V	HP: 1.2V to 1.8V
46 HP	DDR_1V2	1.2V	HP: 1.2V to 1.8V
64 HR	B64_VCO	user	HR: 1.2V to 3.3V
65 HR	3.3V	3.3V	HR: 1.2V to 3.3V
66 HP	B66_VCO	user	HP: 1.2V to 1.8V
67 HP	B67_VCO	user	HP: 1.2V to 1.8V
68 HP	B68_VCO	user	HP: 1.2V to 1.8V

Table 14: Module PL I/O bank voltages

Variants Currently In Production

See also the current available variants on the Trenz Electronic shop page

Trenz shop TEF1001 overview page
English page	German page

Technical Specifications

Absolute Maximum Ratings

Parameter	Min	Max	Units	Reference Document
VIN supply voltage	-0.3	20	V	TPS6217 datasheet Caution with FMC module plugged in: VIN range 11.4V ... 12.6V
Supply voltage for HR I/O banks (VCCO)	-0.500	3.600	V	Xilinx datasheet DS182
Supply voltage for HP I/O banks (VCCO)	-0.500	2.000	V	Xilinx datasheet DS182
I/O input voltage for HR I/O banks	-0.500	VCCO + 0.500	V	Xilinx datasheet DS182
I/O input voltage for HP I/O banks	-0.500	VCCO + 0.500	V	Xilinx datasheet DS182
Reference Voltage pin (VREF)	-0.500	2	V	Xilinx datasheet DS182
Differential input voltage	-0.5	2.625	V	Xilinx datasheet DS182
I/O input voltage for SC CPLD U5	-0.5	3.75	V	Lattice MachXO2 Family datasheet
GTH and GTY transceiver reference clocks absolute input voltage (MGT_CLK0, MGT_CLK2)	-0.500	1.320	V	Xilinx datasheet DS182
GTH and GTY transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage	-0.500	1.260	V	Xilinx datasheet DS182
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J10	-0.3	5.5	V	LTM4676A datasheet
Storage temperature	-40	+100	°C	SML-P11 LED datasheet

Table 16: Module absolute maximum ratings

Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

Parameter	Min	Max	Units	Reference Document
VIN supply voltage	11.4	12.6	V	12V nominal, ANSI/VITA 57.1 power specification for FMC connector
Supply voltage for HR I/O banks (VCCO)	1.140	3.465	V	Xilinx datasheet DS182
Supply voltage for HP I/O banks (VCCO)	1.140	1.890	V	Xilinx datasheet DS182
I/O input voltage for HR I/O banks	–0.500	VCCO + 0.20	V	Xilinx datasheet DS182
I/O input voltage for HP I/O banks	–0.500	VCCO + 0.20	V	Xilinx datasheet DS182
Differential input voltage	-0.2	2.625	V	Xilinx datasheet DS182
I/O input voltage for SC CPLD U5	-0.3	3.6	V	Lattice MachXO2 Family datasheet
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J10	0	3.3V	V	LTM4676A datasheet
Industrial Module Operating Temperature Range	-40	85	°C	Xilinx datasheet DS182
Commercial Module Operating Temperature Range	0	85	°C	Xilinx DS182, Silicon Labs Si5338 datasheet

Table 17: Module recommended operating conditions

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Please check also Xilinx datasheet DS182 for complete list of absolute maximum and recommended operating ratings.

Physical Dimensions

Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.65 mm.
Highest part on PCB: approximately 3 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Figure 5: Module physical dimensions drawing

Revision History

Hardware Revision History

Date	Revision	Notes	PCN	Documentation Link
2018-05-11	02	current available board revision	-	-
2015-12-09	01	First production release	PCN-20180524 TEF1001-01	TEF1001-01

Table 18: Module hardware revision history

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Figure 6: Module hardware revision number

Document Change History

Date	Revision	Contributors	Description
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3589#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]	Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3589#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]	Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3589#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]	Initial document

Table 18: Document change history

Disclaimer

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.

Error rendering macro 'page-info'

Ambiguous method overloading for method jdk.proxy244.$Proxy3589#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]

02 Sept 2017

Trenz Electronic Documentation