- Created by Thorsten Trenz, last modified by John Hartfiel on 03 02, 2020
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Trenz Products |
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EOL of our module series is normaly as long as Xilinx and Intel will offer the FPGA/SoC: Passive components (resistors, capacitors) can be changed on the modules without notification. We use different manufacturer and best prices, but in any case the characteristics which are specified in the schematics are the same. In case other active components will be not longer available, we will replace with footprint compatible equivalent alternatives or we update the PCB to support a equivalent alternatives variant. In case we change such a component, we will create also a new article number, so that you can directly see that something was be updated and we write a PCN |
Xilinx device information can be requested with the 2D Bare code or Lot code on the device package. This can be done via Xilinx App:
Or over web page: In both cases a Xilinx login is needed. |
Downloads / Documents |
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You can lookup for file abbreviations on Documents Naming Conventions. |
PCB document is available on our wiki pages and download area. |
PCB Design |
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The maximum power consumption of a module manly depends on the design which is running on the FPGA. Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to generate power consumption of the developed design with Vivado. Please also observe the TRM of the Trenz Electronic module and the power management of our corresponding carrier boards. |
You can lookup Trenz Electronic Micromodules |
Module pinout files can be generated with our Master Excel Pinout Sheet. You can also use the schematic on our download area. |
See Xilinx Answer Record: AR# 43989 |
Power sequencing of the FPGA/SoC banks and IOs must be still fulfil restrictions from manufacturer data sheet. In most case IOs should be enabled after core voltages are powered on. Some module output voltage can be used to enable carrier power regulator for variable bank powers and connected periphery. See also datasheet power sequencing of the section of the give device: 7 Series:
U/U+ Series:
Xilinx AR# |
Vivado/SDK/SDSoC/PetaLinux |
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Links to Xilinx Release Notes are available on Vivado/SDK/SDSoC: Xilinx Software-Product Update Release Notes and Known Issues |
Reference Designs will be delivered as scripted project file. Vivado Project files will be generated with these scripts. Windows and Linux (since Vivado 2016.4) start up command files are available to generate the project: Project Delivery QuickStart All other options are described on: Vivado Projects - TE Reference Design |
Trenz Electronic Board Part Files will be delivered with the reference designs on our download area.They ca be installed in different ways.
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Xilinx Documentation is available on Xilinx Hompage. Some helpful documents are listed on Vivado/SDK/SDSoC. |
We provide PetaLinux template projects instead of BSPs for our modules. This template are included in our reference design in the subfolder (os/petalinux). They are available on our download area. You can lookup for instructions on: PetaLinux KICKstart |
Xilinx provide a list with supported functionality and devices on: https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html |
Now Vivado check all Beta Devices, but only Devices with valid license are visible. With Beta Device enable, Vivado need longer startup. Select special beta device is supported too. See Xilinx Forum: Synthesis Failure for ZCU102 |
Insufficient external power supply can cause this issue. If power supply is insufficient, module restarts and FPGA content is erased. Vivado did not recognize this. |
Please check following:
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Check if the Quad Enable (QE) bit in the Configuration Register of the flash is set to 1. If the QE-Bit is set or not depends on the last access to the flash.
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