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Table of Contents
Overview
Trenz Electronic TEM0007 module is an industrial-grade FPGA micromodule integrating a Microsemi Polarfire SoC FPGA, Gigabit Ethernet PHY, USB PHY 2.0, one GByte LPDDR4 SDRAM, 64 MByte SPI Flash memory for configuration and operation, and power supply. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.
Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.
Key Features
- SoC/FPGA
- Industrial-grade Microsemi Polarfire SoC MPFS250T-1FCVG484I
- RAM/Storage
- 1 GByte LPDDR4
- 64 MByte SPI Flash Memory
- On Board
- System Controller CPLD
- MAC address serial EEPROM
- Interface
- 10/100/1000 Mbps Gigabit Ethernet PHY
- Highly Integrated Full-Featured Hi-Speed USB 2.0 ULPI Transceiver
- Trenz 4 x 5 module socket connectors (3 x Samtec LSHM series connectors)
- Power
- On-board DC-DC converter
- Dimension
- 40 mm x 50 mm
Block Diagram
Main Components
- Microsemi Polarfire SoC MPFS250T, U2
- 1 GByte LPDDR4 SDRAM, U6
- Integrated 10/100/1000 Mbps Energy Efficient Ethernet Transceiver, U7
- Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver, U11
- Lattice Semiconductor MachXO2 System Controller CPLD, U1
- B2B Connector Samtec Razor Beam, JM1...3
- EEPROM, U10
- Serial NOR Flash, U3
Initial Delivery State
Storage device name | Content | Notes |
---|---|---|
SPI NOR Flash, U3 | Not programmed | - |
EEPROM, U10 | Pre-programmed globally unique MAC | - |
System Controller CPLD, U1 | Standard firmware | - |
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
---|---|---|---|---|
0 | JM2 | 18 | 1.2 V / 1.35 V / 1.5 V / 1.8 V | HSIO dependent on VCCIOD |
0 | JM3 | 16 | 1.2 V / 1.35 V / 1.5 V / 1.8 V | HSIO dependent on VCCIOD |
1 | JM1 | 48 | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V | GPIO dependent on VCCIOB |
1 | JM2 | 36 | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V | GPIO dependent on VCCIOB |
4 | JM1 | 6 | 3.3 V | MSSIO |
4 | JM1 | 6 | 3.3 V | SDIO or MSSIO |
4 | JM1 | 2 | 3.3 V | UART or MSSIO |
5 | JM3 | 4 | - | SGMII (1 pair for TX / 1 pair for RX) |
5 | JM3 | 16 | - | SERDES (4 pairs for TX / 4 pairs for RX) |
5 | JM3 | 4 | - | SERDES CLK (2 pairs for RX) |
JTAG Interface
JTAG access to the TEM0007 SoM through B2B connector JM2.
JTAG Signal | B2B Connector | |
---|---|---|
TMS | JM2-93 | |
TDI | JM2-95 | |
TDO | JM2-97 | |
TCK | JM2-99 | |
JTAGSEL | JM1-89 | Pulled Low: Microsemi Polarfire SoC Pulled High: Lattice MachXO CPLD |
UART Interface
The UART interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.
FPGA Bank 4 | Connected to | B2B | Notes |
---|---|---|---|
MSSIO11 - H2 | UART_RX | JM1 - 92 | |
MSSIO12 - H5 | UART_TX | JM1 - 85 |
SDIO Interface
The SDIO interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.
FPGA Bank 4 | Connected to | B2B | Notes |
---|---|---|---|
MSSIO0 - J1 | SDIO_CLK | JM1 - 27 | |
MSSIO1 - K5 | SDIO_CMD | JM1 - 25 | |
MSSIO2 - H1 | SDIO_DAT0 | JM1 - 23 | |
MSSIO3 - J4 | SDIO_DAT1 | JM1 - 21 | |
MSSIO4 - K4 | SDIO_DAT2 | JM1 - 19 | |
MSSIO5 - J7 | SDIO_DAT3 | JM1 - 17 |
MSSIO Interface
The MSSIO interface is connected from the Polarfire SoC to the B2B connector.
FPGA Bank 4 | Connected to | B2B | Notes |
---|---|---|---|
MSSIO6 - K3 | MIO0 | JM1 - 97 | |
MSSIO7 - H4 | MIO1 | JM1 - 91 | |
MSSIO8 - J6 | MIO2 | JM1 - 99 | |
MSSIO9 - H6 | MIO3 | JM1 - 87 | |
MSSIO10 - J3 | MIO4 | JM1 - 95 | |
MSSIO13 - J2 | MIO5 | JM1 - 93 |
SGMII Interface
The Polarfire Soc provides two SGMII interfaces whereby one interface is connected to the B2B connector.
FPGA Bank 5 | Connected to | B2B | Notes |
---|---|---|---|
U2 - N8 | SGMII1_OUT_N | JM3 - 1 | |
U2 - M7 | SGMII1_OUT_P | JM3 - 3 | |
U2 - K7 | SGMII1_IN_N | JM2 - 2 | |
U2 - K6 | SGMII1_IN_P | JM2 - 4 |
MGT Lanes
There are four MGT (Multi Gigabit Transceiver) lanes and two two clocks connected between the B2B connector JM3 and the Polarfire SoC bank 5. Each MGT lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, signal schematic name, and board-to-board pin connection:
Lane | Schematic | B2B | Note |
---|---|---|---|
0 | XCVR_RX0_P | JM3-26 | |
0 | XCVR_RX0_N | JM3-28 | |
0 | XCVR_TX0_N | JM3-25 | |
0 | XCVR_TX0_P | JM3-27 | |
1 | XCVR_RX1_P | JM3-20 | |
1 | XCVR_RX1_N | JM3-22 | |
1 | XCVR_TX1_P | JM3-19 | |
1 | XCVR_TX1_N | JM3-21 | |
2 | XCVR_RX2_P | JM3-14 | |
2 | XCVR_RX2_N | JM3-16 | |
2 | XCVR_TX2_P | JM3-13 | |
2 | XCVR_TX2_N | JM3-15 | |
3 | XCVR_RX3_P | JM3-8 | |
3 | XCVR_RX3_N | JM3-10 | |
3 | XCVR_TX3_P | JM3-7 | |
3 | XCVR_TX3_N | JM3-9 | |
CLK | XCVR_CLK0_P | JM3-33 | |
CLK | XCVR_CLK0_P | JM3-31 | |
CLK | XCVR_CLK1_P | JM3-32 | |
CLK | XCVR_CLK1_N | JM3-34 |
Gigabit Ethernet
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY SGMII interface is connected to the Polarfire SoC.
ETH Pin | Connected to | B2B | Notes |
---|---|---|---|
MDIP[0] - 28 | PHY_MDI0_P | JM1 - 4 | |
MDIN[0] - 27 | PHY_MDI0_N | JM1 - 6 | |
MDIP[1] - 24 | PHY_MDI1_P | JM1 - 10 | |
MDIN[1] - 23 | PHY_MDI1_N | JM1 - 12 | |
MDIP[2] - 22 | PHY_MDI2_P | JM1 - 16 | |
MDIN[2] - 21 | PHY_MDI2_N | JM1 - 18 | |
MDIP[3] - 18 | PHY_MDI3_P | JM1 - 22 | |
MDIN[3] - 17 | PHY_MDI3_N | JM1 - 24 |
System Controller CPLD I/O Pins
The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
CPLD Pin | Connected to | B2B | Notes |
---|---|---|---|
TDO - 1 | TDO | JM2 - 97 | |
TDI - 32 | TDI | JM2 - 95 | |
TCK - 30 | TCK | JM2 - 99 | |
TMS - 29 | TMS | JM2 - 93 | |
JTAGENB - 26 | JTAGSEL | JM1 - 89 | |
- 11 | SC_EN1 | JM1 - 28 | |
- 12 | SC_PGOOD | JM1 - 30 | |
- 14 | SC_nRST | JM2 - 18 | |
- 17 | NOSEQ | JM1 - 7 |
USB Interface
USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Polarfire SoC. I/O voltage is fixed at 3.3 V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U12).
PHY Pin | Connected to | B2B | Notes |
---|---|---|---|
DP - 18, | OTG-D_P | JM3 - 47 | USB data line |
DM - 19 | OTG-D_N | JM3 - 49 | USB data line |
CPEN - 17 | VBUS_EN | JM3 - 53 | External USB power switch |
VBUS - 22 | VBUS | JM3 - 55 | |
ID - 23 | ID | JM3 - 51 |
Test Points
Test Point | Signal | Connected to | Notes |
---|---|---|---|
1 | +3.3V | High-Side Switch, U14 | |
2 | +2.5V | Voltage Regulator, U21 | |
3 | +2.5V_XCVR | Voltage Regulator, U22 | |
4 | +1.8V | Voltage Regulator, U20 | |
5 | +1.8V_VDD | High-Side Switch, U13 | |
6 | +1.1V_LPDDR4 | Voltage Regulator, U18 | |
7 | +1.0V | Voltage Regulator, U19 | |
8 | VDDAUX1 | Power Switch, U16 | |
9 | AVDD18 | Voltage Regulator, U7 | |
10 | AVDD33 | Inductor, L6 | |
11 | DVDD1V0 | Voltage Regulator, U7 | |
12 | F_TRSTB | FPGA Bank 3 |
On-board Peripherals
Chip/Interface | Designator | Notes |
---|---|---|
System Controller CPLD | U1 | |
Gigabit Ethernet | U7 | |
USB PHY | U11 | |
LPDDR4 SDRAM | U6 | |
EEPROM | U10 | |
SPI Flash Memory | U3 | |
Oscillators | U4...5, U12 |
System Controller CPLD
The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
Gigabit Ethernet
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY SGMII interface is connected to the Polarfire SoC. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U8).
SoC U2 | Signal Name | ETH | Signal Description | |
---|---|---|---|---|
Bank 5 - N6 | SGMII0_IN_P | U7 - 1 | SGMII Data Positive | |
Bank 5 - N7 | SGMII0_IN_N | U7 - 2 | SGMII Data Negativ | |
Bank 5 - L5 | SGMII0_OUT_P | U7 - 4 | SGMII Data Positive | |
Bank 5 - L6 | SGMII0_OUT_N | U7 - 5 | SGMII Data Negativ | |
Bank 2 - D3 | ETH_MDC | U7 - 7 | Management Data Clock | |
Bank 2 - C2 | ETH_MDIO | U7 - 8 | Management Date I/O | |
Bank 2 - E5 | ETH_RST | U7 - 16 | Hardware Reset | |
Bank 1 - AA16 | PHY_LED0 | U7 - 14 | LED Output | via voltage-level translator |
Bank 1 - Y16 | PHY_LED1 | U7 - 13 | LED Output | via voltage-level translator |
Bank 1 - Y14 | PHY_LED2 | U7 - 12 | LED Output | via voltage-level translator |
USB PHY
Hi-speed USB ULPI PHY (U11) is provided with USB3320 from Microchip. The ULPI interface is connected to the Polarfire SoC via MSSIO14...25 bank 2. The I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U12).
Bank 2 | Signal Name | USB | Signal Description |
---|---|---|---|
U2 - G4 | OTG-STP | U11 - 29 | Stop |
U2 - G5 | OTG-NXT | U11 - 2 | Next |
U2 - F1 | OTG-DIR | U11 - 31 | Direction |
U2 - G2 | OTG-CLK | U11 - 1 | Clock |
U2 - F2 | OTG_DATA0 | U11 - 3 | ULPI bi-directional data bus |
U2 -E1 | OTG_DATA1 | U11 - 4 | ULPI bi-directional data bus |
U2 -G3 | OTG_DATA2 | U11 - 5 | ULPI bi-directional data bus |
U2 -F5 | OTG_DATA3 | U11 - 6 | ULPI bi-directional data bus |
U2 - D1 | OTG_DATA4 | U11 - 7 | ULPI bi-directional data bus |
U2 -D2 | OTG_DATA5 | U11 - 9 | ULPI bi-directional data bus |
U2 -F6 | OTG_DATA6 | U11 - 10 | ULPI bi-directional data bus |
U2 - F3 | OTG_DATA7 | U11 - 13 | ULPI bi-directional data bus |
U2 - E4 | OTG-RST | U11 - 27 | Reset |
LPDDR4 SDRAM
The TEM0007 SoM has a one GByte volatile LPDDR4 SDRAM IC for storing user application code and data.
- Part number: IS43LQ32256A-062BLI
- Supply voltage: +1.8 V / +1.1 V
- Speed: 1600 MHz
- Temperature: Industrial (-40°C to +85°C)
EEPROM
There is a 2 Kbit EEPROM provided on the module TEM0007 with a pre-programmed globally unique MAC.
MSSIO Pin | Schematic | U10 Pin | Notes |
---|---|---|---|
26 | I2C_SCL | SCL - 1 | |
27 | I2C_SDA | SDA - 3 |
MSSIO Pin | I2C Address | Designator | Notes |
---|---|---|---|
MSSIO26...27 | 0x50 | U10 |
SPI Flash Memory
The TEM0007 is equipped with a MT25QU512ABB8E12-0SIT flash memory chip, U3, which provided storage for FPGA configuration files. After configuration, the remaining free memory can be used for application data storage.
Polarfire SoC Pin | Schematic | U3 Pin | Notes |
---|---|---|---|
SCK_3 - E6 | SPI_SCK | CLK - B2 | |
SS_3 - G7 | SPI_SS | CS# - C2 | |
SDO_3 - F7 | SPI_SDO | DI/IO0 - D3 | |
SDI_3 - H10 | SPI_SDI | DO/IO1 - D2 | |
SPI_EN_3 - H11 | SPI_EN | - |
Oscillators
Designator | Description | Frequency | Note |
---|---|---|---|
U4 | MSS REFCLK | 125 MHz | |
U5 | SERDES CLK | 125 MHz | |
U12 | USB | 52 MHz |
Power and Power-On Sequence
Power Supply
Power supply with minimum current capability of 3 A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
---|---|
VIN | TBD* |
3.3VIN | TBD* |
* TBD - To Be Determined
Power Distribution Dependencies
Power-On Sequence
Create DrawIO object here: Attention if you copy from other page, objects are only linked.
Voltage Monitor Circuit
Create DrawIO object here: Attention if you copy from other page, objects are only linked.
Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | Direction | Notes |
---|---|---|---|---|
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from the carrier board |
3.3VIN | 13, 15 | - | Input | Supply voltage from the carrier board |
3.3VIN | - | 91 | Output | JTAG reference voltage |
+1.8V | 39 | - | Output | Internal +1.8V voltage level |
VCCIOB | - | 1, 3 | Input | General purpose I/O bank voltage |
VCCIOD | - | 7, 9 | Input | High speed I/O bank voltage (max. +1.8 V) |
+3.3V | - | 10, 12 | Output | Internal +3.3 V voltage level |
Bank Voltages
Bank | Schematic Name | Voltage | Notes |
---|---|---|---|
Bank 0 HSIO | VCCIOD | Variable | max. voltage +1.8 V |
Bank 1 GPIO | VCCIOB | Variable | max. voltage +3.3 V |
Bank 2 MSSIO | +3.3V | +3.3 V | |
Bank 3 | +1.8V | +1.8 V | |
Bank 4 MSSIO | +3.3V | +3.3 V | |
Bank 5 | +3.3V | +3.3 V | |
Bank 6 MSS DDR | +1.1V_LPDDR4 | +1.1 V |
Board to Board Connectors
These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.
4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.
- 2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
- 1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)
Connector Mating height
When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height
Order number | Connector on baseboard | compatible to | Mating height |
---|---|---|---|
23836 | REF-189016-01 | LSHM-150-02.5-L-DV-A-S-K-TR | 6.5 mm |
LSHM-150-03.0-L-DV-A-S-K-TR | LSHM-150-03.0-L-DV-A-S-K-TR | 7.0 mm | |
23838 | REF-189016-02 | LSHM-150-04.0-L-DV-A-S-K-TR | 8.0 mm |
LSHM-150-06.0-L-DV-A-S-K-TR | LSHM-150-06.0-L-DV-A-S-K-TR | 10.0mm | |
26125 | REF-189017-01 | LSHM-130-02.5-L-DV-A-S-K-TR | 6.5 mm |
LSHM-130-03.0-L-DV-A-S-K-TR | LSHM-130-03.0-L-DV-A-S-K-TR | 7.0 mm | |
24903 | REF-189017-02 | LSHM-130-04.0-L-DV-A-S-K-TR | 8.0 mm |
LSHM-130-06.0-L-DV-A-S-K-TR | LSHM-130-06.0-L-DV-A-S-K-TR | 10.0mm |
The module can be manufactured using other connectors upon request.
Connector Speed Ratings
The LSHM connector speed rating depends on the stacking height; please see the following table:
Stacking height | Speed rating |
---|---|
12 mm, Single-Ended | 7.5 GHz / 15 Gbps |
12 mm, Differential | 6.5 GHz / 13 Gbps |
5 mm, Single-Ended | 11.5 GHz / 23 Gbps |
5 mm, Differential | 7.0 GHz / 14 Gbps |
Current Rating
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).
Connector Mechanical Ratings
- Shock: 100G, 6 ms Sine
- Vibration: 7.5G random, 2 hours per axis, 3 axes total
Manufacturer Documentation
Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit |
---|---|---|---|---|
VIN | Supply voltage | -0.3 | 6.0 | V |
3.3VIN | Supply voltage | -0.3 | 3.6 | V |
VCCIOB | I/O bank voltage | -0.5 | 3.6 | V |
VCCIOD | I/O bank voltage | -0.5 | 2.0 | V |
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN | 2.7 | 5.5 | V | See EN6363Q, EP53A7LQI, and EP53A7HQI datasheets. |
3.3VIN | 3.14 | 3.46 | V | See 88E1512 datasheet. |
VCCIOB | 1.14 | 3.465 | V | See MPFS250T datasheet. |
VCCIOD | 1.14 | 1.89 | V | See MPFS250T datasheet. |
Physical Dimensions
Module size: 40 mm × 50 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.74 mm.
Currently Offered Variants
Trenz shop TE0728 overview page | |
---|---|
English page | German page |
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
---|---|---|---|
2020-05-26 | 01 | Inital Release | REV01 |
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
Date | Revision | Contributor | Description |
---|---|---|---|
| |||
-- | all |
|
Disclaimer
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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
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