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Table of Contents

Table of Contents

Overview

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Refer to https://wiki.trenz-electronic.de/display/PD/TE0726+TRM for online version of this manual and additional technical documentation of the product.

The Trenz Electronic TE0726 "ZynqBerry" is a industrial-grade Raspberry Pi form-factor compatible FPGA SoM (System on Module) based on Xilinx Zynq-7010 SoC (XC7Z010 System on Chip) with up to 512 MByte DDR3L SDRAM, 4 x USB 2.0 ports, 10/100 Mbit Ethernet port and 16 MByte Flash memory.

Key Features

Xilinx Zynq XC7Z010-1CLG225C
- REV3: DDR3L SDRAM (512 MByte)
- REV2: DDR3L SDRAM (128 - 512 MByte)
- REV1: LPDDR2 SDRAM (64 MByte)
16 MByte Flash
Raspberry Pi Model 2 form factor
LAN9514 USB hub with 10/100 Ethernet
- 4 x USB 2.0 with power switches
- 10/100 Mbit Ethernet RJ45
Micro SD card slot with card-detect switch
HDMI connector
DSI connector (Display)
CSI-2 connector (Camera)
HAT header with 26 I/Os
Micro-USB
- power input
- USB UART
- JTAG ARM- and FPGA-Debug
3.5 mm stereo audio socket (PWM audio output only)
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Block Diagram

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Main Components

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Xilinx Zynq XC7Z010 All Programmable SoC, U1
512 MByte DDR3L SDRAM, U8
Lattice Semiconductor MachXO2 System Controller CPLD, U11
Dual high-speed USB to multipurpose UART/FIFO, U3
2 Kbit Microwire compatible serial EEPROM, U6
Low-power, programmable oscillator @ 12.000000 MHz, U7
Ultra-low capacitance double rail-to-rail ESD protection diode ,U4
Micro-USB 2.0 B receptacle, J1
Green LED (GLED), D1
Red LED (RLED), D2
DSI LCD connector, J4
JTAGENB, when low, TDO, TDI, TMS and TCK function as GPIOs, J15
Fiducial mark PM2
External I²C bus with interrupt signal and power line, J2
Low-voltage 4-channel I²C and SMBus multiplexer with interrupt logic, U10
2x20 pin 2.54 GPIO header, J8
128 Mbit (16 MByte) 3.0V SPI Flash memory, U5
USB 2.0 Hub and 10/100 Ethernet controller, U2
External reset
2 Kbit Microwire compatible serial EEPROM, U9
PUDC of Zynq, active low enables internal pull-ups during configuration on all SelectIO pins
Dual USB A receptacle, J12. Also fiducial mark PM1
Dual USB A receptacle, J11
Low power programmable oscillator @ 25.000000 MHz, U13
Molex’s miniature traceability S/N pad for low-cost, unique product identification
RJ-45 Ethernet connector with 10/100 integrated magnetics, J10. Also fiducial mark PM3
3.5mm RCA audio jack, J7
1A PowerSoC synchronous buck regulator with integrated inductor (3.3V), U20
1A PowerSoC synchronous buck regulator with integrated inductor (1.8V), U19
ZIF FFC/FPC CSI-2 camera connector, J3
HDMI connector, J6
Common mode filter with ESD protection, D8
Common mode filter with ESD protection, D9
1A PowerSoC synchronous buck regulator with integrated inductor (1.35V), U16
Additional external +5V power supply connector, J5
Highly integrated full featured hi-speed USB 2.0 ULPI transceiver, U18
Low-power programmable oscillator @ 33.333333 MHz, U14
Ultra-low supply current voltage monitor with optional watchdog, U22
Fiducial mark PM4
Micro SD memory card connector with detect switch, J9
JTAG interface, TP1 (TDI), TP3 (TDO), TP5 (TCK), TP7 (TMS)
1A PowerSoC synchronous buck regulator with integrated inductor (1.0V), U17
Fiducial mark PM6
0.5A dual channel current-limited power switch, U15
0.5A dual channel current-limited power switch, U21
Fiducial mark PM5

Initial Delivery State

Up on delivery from Trenz Electronic System Controller CPLD is programmed with the standard firmware and FTDI FT2232H EEPROM contains pre-programmed Digilent license needed by Xilinx software tools for JTAG access, all other programmable devices are empty.

Signals, Interfaces and Pins

Camera Serial Interface (CSI-2)

The TE0726-03 module has CSI-2 specification compatible serial camera interface routed from Zynq SoC bank 34 to the connector J3.

...

Display Serial Interface (DSI)

The TE0726-03 module has MIPI Alliance DSI specification compatible serial display interface routed from Zynq SoC bank 35 to the connector J4.

...

See also section FPGA IO Banks Pin Mapping, pins DSI_XA and DSI_XB.

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HDMI Interface

HDMI interface is routed from Zynq SoC bank 34 to the external connector J6 via EMI4192 ESD protector/EMI filters.

...

Audio Output

Pulse-width modulated stereo audio output is routed from Zynq SoC bank 34 to external 3.5mm socket J7.

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SD Card Socket

Micro SD memory card connector J9 with detect switch is connected to the Zynq Soc PS MIO bank 500. See also section Default MIO Mapping.

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FPGA IO Banks Pin Mapping

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Header J8 Interface Mapping

26 PL IO and 2 MIO IOs over I2C mux. All Bank IO voltages are 3.3V.

...

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Default MIO Mapping

Bank 500 MIOs

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MIO

...

MIO0_INT

...

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Bank 501 MIOs

...

On-board LEDs

There are two LEDs on TE0726 module:

...

LED

...

Color

...

Notes

...

D2

...

Red

...

4

...

CPLD bank 3.

On-board Peripherals

System Controller CPLD

There is a System Controller CPLD chip LCMXO2-256HC from Lattice Semiconductor on-board. Refer to the TE0726 CPLD for more information.

Quad SPI Flash Memory

On-board QSPI flash memory (U5) on the TE0726 is provided by Cypress Semiconductor Serial NOR Flash Memory S25FL127SABMFV10 with 128 Mbit (16 MByte) storage capacity connected to the PS MIO bank (MIO1 ... MIO6) of the Zynq SoC. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq PS MIO-bank allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

DDR3L SDRAM

The TE0726 SoM is equipped with one DDR3L-1600 SDRAM module with 1 GByte memory density. The SDRAM module is connected to the Zynq SoC's PS DDR controller with 16-bit data bus-width.

Clocking

...

Signal Name

...

Default Frequency

...

Destination IC

...

Notes

...

33.333333 MHz

...

U1

...

C7

...

12.000000 MHz

...

U3

...

3

...

FT2232H oscillator input.

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Hi-speed USB 2.0 and 10/100 Mbit Ethernet

The TE0726-03 has on-board SMSC LAN9514 controller featuring USB 2.0 hub and 10/100 Mbit Ethernet controller. USB hub has four downstream ports and one upstream port, fully compliant with Universal Serial Bus Specification Revision 2.0. HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) compatible. Upstream port is connected to the SMSC USB3320 hi-speed USB 2.0 ULPI transceiver which has full support for the optional On-The-Go (OTG) protocol.

High-Performance 10/100 Ethernet controller integrated into the same LAN9514 IC is fully compliant with IEEE802.3/802.3u standards, has integrated Ethernet MAC and PHY and supports both 10BASE-T and 100BASE-TX media.

256-byte EEPROM is connected via Microwire to the LAN9514 chip to store MAC address.

USB to JTAG/UART

The TE0726-03 has on-board high-speed USB 2.0 to UART/FIFO FT2232H controller from FTDI with external connection to micro-USB connector J1. There is also a 256-byte EEPROM wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools.

Warning
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

4-Channel I2C Multiplexer

Zynq MIO pin 48 (MUX_SCL) and pin 49 (MUX_SDA) are connected to the 4-channel I²C multiplexer chip TCA9544A from Texas Instruments having I²C address of 0x70. It has four slave I²C channels which are routed as follows:

...

Channel

...

Connected To

...

0

...

Connector J8, pin 27 (ID_SDA) and pin 28 (ID_SCL).

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1

...

DSI connector J4, pin 12 (DSI_SDA) and pin 11 (DSI_SCL).

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2

...

HDMI connector J6, pin 16 (SDA) and pin 15 (SCL).

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3

...

CSI-2 camera connector J3, pin 14 (CSI_SDA) and pin 13 (CSI_SCL).

Each slave channel of TCA9544A has its own dedicated interrupt signal in order for the master to detect an interrupt on the INT output pin that can result from any of the slave devices connected to the INT0-INT3 input pins.

Boot Process

Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader.

At least FSBL must be loaded from on-board SPI Flash, later all boot process can continue from SD Card. The easiest solution is to let FSBL to load bitstream and u-boot from SPI Flash, and then let u-boot to load Linux or any other OS image from SD Card.

Power and Power-On Sequence

Power Consumption

TE0726 needs one single power source via Micro USB2.0 B socket J1. However, it is recommended to not use any USB equipment below USB standard 2.0 to power the module. Also two-pin header J5 can be used as alternative to feed the 5V power supply voltage.

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

To power-up a module, 5.0V power supply with minimum current capability of 1A is recommended.

Power Distribution Dependencies

There is no specific power-on sequence, except to achieve minimum current draw, I/Os should be 3-stated at power-on.

There are following dependencies how the power supply voltage (5V nominal) is distributed to the on-board DC-DC converters.

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Power Rails and Bank Voltages

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Rail/Bank

...

Voltage

...

Notes

...

34

...

3.3V

...

1.8V

...

PL HR I/O bank.

...

502

...

1.35V

...

Variants Currently in Production

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RAM

...

Technical Specifications

If TE0726 module is powered by micro-USB connector J1 V_BUS pin, which voltage level is controlled by supplying host according to the USB standards and should be 5V, there is not much user can control here if using standard USB equipment. However, user can also power the module by applying voltage to the J5 connector from other external sources. In both cases following maximum voltage ratings apply.

Absolute Maximum Ratings

...

Parameter

...

Units

...

Notes

...

Power supply voltage

J1: USB_V_BUS, J5: 5V

...

4.75

...

5.25

...

V

...

Storage temperature

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-55

...

+125

...

°C

...

See also the Xilinx datasheet DS187 for more information about absolute maximum ratings.

Recommended Operating Conditions

...

Power supply voltage

J1: USB_V_BUS, J5: 5V

...

4.75

...

°C

...

The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

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Physical Dimensions

Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.

All dimensions are shown in millimeters. Additional sketches, drawings and schematics can be found here.

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Weight

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Revision History

Hardware Revision History

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Notes

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01

...

-

...

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

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Document Change History

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Date

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Revision

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Contributors

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Description

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Custom_table_size_100

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Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"

Template Change history:

Version	Changes	Author
4.2	Changes Xilinx to AMD	ED
4.1	Minor changes Notes Tables	ED
4.0	Rework for smaller TRM which can be generated faster Reduce Signal Interfaces Pin Reduce On Board Periphery Reduce Power Move Configuration Signals from Overview to own section	JH
3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma
3.11	update "Recommended Operating Conditions" section
3.1	New general notes for temperature range to "Recommended Operating Conditions"
3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hybrid, Evalboard, Carrier)
3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)
3.00	→ separation of Carrier/Module and evaluation kit TRM
2.15	add excerpt macro to key features
2.14	add fix table of content add table size as macro

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables

Scroll Title

anchor	Table_tablename
title-alignment	center
title	Text

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Example	Comment
1	2

The anchors of the Scroll Title should be named consistent across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchor from external : <page url>#<pagename without space characters>-<anchorname>

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

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Download PDF version of this document.

Overview

The Trenz Electronic TE0726 is an industrial/extended grade module based on AMD Zynq 7 Series. It is Raspberry Pi form-factor compatible.

Refer to http://trenz.org/te0726-info for the latest online version of this manual and other available documentation.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples for different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt

SoC/FPGA/Module
- Package: CLG225
- Device: Z-7007S, Z-7010, ¹⁾
- Temperature ranges: Commercial / Extended / Industrial ¹⁾
- Speed grades: -3, -2, -1 ¹⁾
RAM/Storage
- 512 MByte DDR3L ECC RAM ¹⁾
- 16 MByte QSPI Flash ¹⁾
- 2 KBit EEPROM for FTDI
- 2 KBit EEPROM for Ethernet & USB HUB
On Board
- System Controller CPLD
- USB ULPI Transceiver
- 10/100 Ethernet Transceiver with USB hub
- USB to JTAG / UART FTDI
Interface
- 1x Micro USB (UART/JTAG)
- 4x USB 2.0
- 1x microSD Card socket
- 1x Boot Select DIP switch
- 1x Ethernet RJ45 socket
- 1x TRRS Audio Jack 3.5mm with microphone (PWM audio only)
- 1x HDMI Connector
- 1x CSI-2 Connector (Camera Serial Interface)
- 1x DSI Connector (Display Serial Interface)
- 1x5 Pin Header for I²C
- 2x20 Pin Header with 26 GPIO, 1x I²C , 5 and 3.3 V
- 3 additional Pinheaders for CPLD access, Reset and PUDC (SoC Boot IO State) changes
Power
- via Micro USB
- via 5V Pin header
Dimension
- 56 mm x 85 mm, like Raspberry Pi
Notes
¹⁾Depends on assembly variant

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	TE0726 block diagram

Scroll Ignore

draw.io Diagram

border	true

diagramName	Figure_OV_BD_TE0726_04
simpleViewer	false
width
links	auto
tbstyle	hidden
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lbox	true
diagramWidth	641
revision	1

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Main Components

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Note
For more information regarding how to add board photos, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	TE0726 main components

Scroll Ignore

draw.io Diagram

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diagramName	Figure_OV_MC_TE0726-04
simpleViewer	false
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lbox	true
diagramWidth	639
revision	1

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Image Added

AMD 7 Series Zynq, U1
DDR3L ECC RAM, U8
SPI Flash, U5
System Controller CPLD, U11
FTDI USB to multipurpose JTAG/FIFO, U3
USB Transceiver, U18
Ethernet Transceiver LAN9514 with 4 port USB Hub , U2
EEPROM, U6 , U9
I²C Multiplexer, U10
Power Supply, U16, U17, U19, U20
USB power switch, U15 , U21
Oscillator, U14 , U13 , U7
LED, D1 , D2
Micro USB B receptacle, J1
microSD card, J9
2x USB A, J11 , J12
RJ-45 Ethernet connector, J10
HDMI connector, J6
DSI LCD connector, J4
CSI camera connector, J3
3.5mm RCA audio jack, J7
+5V Power Connector, J5
Boot DIP switch, S1
JTAG Port select header, J15
Boot IO State select header, J14
Externer reset header, J13
2x20 pin header, J8

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

orientation	portrait
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repeatTableHeaders	default
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sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
Quad SPI Flash	not programmed
EEPROM FTDI	preprogrammed
EEPROM ETH	not programmed
System Controller CPLD	preprogrammed

Signals, Interfaces and Pins

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Note
Table with all connectors and Designator List of different interfaces per connector IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors

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Connector Type	Designator	Interface	IO CNT	Notes
2x 20 2.54 mm Pin Header	J8	GPIO (HR)	26
2x 20 2.54 mm Pin Header	J8	I²C	2	Multiplexer U10
2x 2.54 mm Pin Header	J15	JTAG select	1	SoC or SC select
2x 2.54 mm Pin Header	J14	Boot IO State select	1
2x 2.54 mm Pin Header	J13	External reset	1
2x USB A stacked	J11, J12	USB 2.0	12	To USB PHY (ULPI)
5x 2.54 mm Pin Header	J2	I²C	2	Multiplexer U10, I²C shared with J4
5x 2.54 mm Pin Header	J2	Interrupt	1	Multiplexer U10
DIP switch	S1	Boot select	1	Shared with SPI
FCC	J4	MIPI DSI	6 (3 pairs)
FCC	J4	I²C	2	Multiplexer U10
FCC	J3	I²C	2	Multiplexer U10
FCC	J3	MIPI CSI-2	8 (4 pairs)
HDMI	J6	HDMI	8 (4 pairs)
HDMI	J6	I²C	2	Multiplexer U10
HDMI	J6	Interrupt	1	Multiplexer U10
Micro-USB 2.0 B	J1	JTAG	2 (1 pair)	SoC or SC selectable
microSD Card	J9	Interrupt	1	Multiplexer U10
microSD Card	J9	SD	5
RJ-45 Ethernet	J10	10/100 ETH	12	To USB PHY (ULPI)
TRRS 3.5 mm	J7	RCA Audio	2
TRRS 3.5 mm	J7	RCA Mic	1

Test Points

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Test Point	Signal	Notes
TP1	TDI
TP2	3.3V
TP3	TDO
TP4	1.8V
TP5	TCK
TP6	1.0V
TP7	TMS
TP8	1.35V
TP9	5V
TP10	GND
TP11	GND
TP12	GND
TP13	GND
TP14	POR B	Zync SoC reset signal
TP15	PG_1.35V	Power good signal
TP16	PG_1.8V	Power good signal
TP17	PG_3.3V	Power good signal
TP18	PG_1.0V	Power good signal
TP19	PUDC	Zynq SoC IO State during boot process
TP20	SPI0_DQ3/M0	Boot source select signal

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

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Chip/Interface	Designator	Connected To	Notes
DDR3L RAM	U8	Zynq SoC DDR Interface PS Bank 502
System Controller CPLD	U11	Zynq SoC MIO Bank 35 MIDI DSI J4 MIDI CSI J3 FTDI U7 LEDs
USB-PHY	U18	Zynq SoC MIO and Zynq SoC USB ULPI
USB Ethernet Hub	J10	USB PHY USB A connectors J11 and J12 Power switch for USB A connectors U15, U21 ETH connector J10 EEPROM U9
FTDI	U3	JTAG to System Controller and Zynq SoC EEPROM U6
I²C Expander	U10	Zynq MIO (Bus master) DDR3L via Voltage Bridge U12 shared with MIDI CSI J3 MIDI DSI J4 and Pin Header J2 HDMI socket J6 Pin header J8
I²C Interrupts	U10	Zynq MIO (Bus master) microSD Card socket J9 inseration detection HDMI J6 inseration detection Pin header J2
Oscillator	U14	Zynq SoC - PS	33.3 MHz
Oscillator	U9	USB PHY	25 MHz
Oscillator	U7	FTDI	12 MHz

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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

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title-alignment	center
title	Controller signal.

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Connector	Signal Name	Direction¹⁾	Description
S1	SPI0_DDQ3 / MO	IN	Boot source switch, SPI flash or SD Card
J13	EXTRST , POR_B , nRST	IN	Reset Zynq SoC
J14	PUDC	IN	State of Zynq SoC IO lines during boot
J15	JMODE , BDBUS7	IN	JTAG endpoint selction, System Controller or Zynq SoC

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

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List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power

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Power Rail Name/ Schematic Name	Connector + Pin	Direction¹⁾	Notes
USB_B_Vbus	J1	IN	Default power supply 5V
5V	J5.1	IN/OUT	2x Pin Header, intended for alternative powering
5V	J2.1 J8.2 , J8.4	OUT	5x Pin Header 2x 20 Pin Header
5V_HDMI	J6.18	OUT	HDMI, reverse current protection diode D11
V_BUS_A , V_BUS_B , V_BUS_C , V_BUS_D	J11.A1 , J11.B1 , J12.A1 , J12.B1	OUT	2x USB A socket
3.3V	J8.1 , J8.17 J3.15 J4.15 J9.4	OUT	2x 20 Pin Header FCC CSI FCC DSI microSD Card socket

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.

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Sequence

Net name

Recommended Voltage Range

Pull-up/down

Description

Notes

1

USB_B_Vbus

5V (± 5 %)

-

Main Power supply via Micro-USB J1.

Main module power supply. 0.5 A minimum. Power consumption depends mainly on design and cooling solution. If more current is needed use J5 for external power supply.

2

3.3V

-

Module generated output voltage.

3

-

External components which are connected to J8 should be powered up with 3.3V from module.

See link:
https://docs.amd.com/v/u/en-US/ds187-XC7Z010-XC7Z020-Data-Sheet
, page 8 "PL Power‐On/Off Power Supply Sequencing" for PL IO usage

Technical Specifications

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List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings ^*)

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Power Rail / Schematic Name	Description	Min	Max	Unit
USB_B_Vbus	Determined through "USB 2.0 VBUS Max Limits"	4.75	5.5	V
5V	Determined through "USB 2.0 VBUS Max Limits"	4.75	5.5	V

^*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

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Parameter	Min	Max	Units	Reference Document
USB_B_Vbus	4.75	5.25	V	Schematic of this board. SCH-TE0726-04-41C94-A.PDF page 3, table "Supported Voltage Ranges"
5V	4.75	5.25	V	Schematic of this board. SCH-TE0726-04-41C94-A.PDF page 3, table "Supported Voltage Ranges"

Physical Dimensions

Module size: 85 mm × 56 mm. Please download the assembly diagram for exact numbers.

PCB thickness: 1.57 mm ± 10 %.

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guideline" .

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title	Physical Dimension

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Image Added

Currently Offered Variants

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

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title	Trenz Electronic Shop Overview

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cellHighlighting	true

Trenz shop TE0726 overview page
English page	German page

Revision History

Hardware Revision History

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hidden	true
id	Comments

Set correct links to download Carrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD
Example:
Date Revision Changes Documentation Link
2020-11-25 REV02
Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
REV02

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title	Board hardware revision number.

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draw.io Diagram

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Date	Revision	Changes	PCN Link	Documentation Link
2023-06-10	04	Page Numbers refer to the schematic for this revision EOL components U16, U17 , U19, U20 (EN5311QI) were replaced by MPM3834CGPA Added MIC bias power L12, C114 , R151 (Page 16) Added Legal notices (Page 1) Added power diagram (Page 4) Added S1 switch and R152 for "JTAG only mode" enable (Page 8) The signals were renamed: SPI-DQ0/M0 ---> SPI-DQ0/M3 SPI-DQ3/M3 ---> SPI-DQ3/M0 ECC function has been added for U8 (Page 11) Added I2C level shifter U12 for DDR3 ECC function (Page 11) Added Buffers U24, U25 to match the level of signals (Page 6) Added Diode D7, resistors R155, R160 EOL components L1, L2, L3, L4, L6, L7, L9, L10 BKP0603HS121-T replaced by MPZ0603S121HT000 EOL components D8, D9 SP5001-04TTG replaced by EMI8042MUTAG Resistors R80-R82 replaced by 10 kOhm (was 1k43) Added Testpoints TP15 - TP20 The type of testpoints TP1 - TP14 was updated. Diameter changed from 0.8 mm to 1 mm CEC function is not supported. L11 was removed. C127, D5, R140, R42 are DNP Power-up sequencing was updated for new DC-DC supplies Capacitors C29, C32, C33 replaced by 470 nF (was 100 nF)	PCN-20230619 TE0726-03 to TE0726-04 Hardware Revision Change	TE0726-04
2021-01-21	03	Change DDR3 RAM (U8) from IM4G16D3FABG-125I to IS43TR16256BL-125KBLI Clock Revision Change (U7, U14) from SiT8008AI-... to SiT8008BI-... Clock Revision Change (U13) from SiT8008AI-... to SiT8008BI-... LEDs D1 and D2 changed to 19-213/G6C-BM1N2/DT and 19-213/R6C-AL1M2VY/3T Set S/N to not fitted	PCN-20210121 TE0726-03 DDR3 Change and Product Update	TE0726-03
2019-04-08	03	VBUS Resistor R94 replaced by 10 kOhm (was 12k1)	-	TE0726-03
2016-05-06	03	Introduced new variants: Default with DDR3L 128 Mb TE0726-03M with DDR3L 512 Mb TE0726-03L with DDR3L 128 Mb, without usb's, eth_phy, RJ-45, CSI, DSI, HDMI and 3.5mm jack connectors Changed FTDI to 56 pins package Moved LED's into Raspberry Pi 3 layout Replaced POWER connector on right angle connector Corected conection PUDC pin Replace HDMI, DSI/CSI connector, USB stacked connectors, RJ-45, power connector)	-	TE0726-03
2016-01-26	02	CSI CLK line moved to MRCC pin, CSI lanes swap CSI camera GPIO moved to MIO GPIO RPi GPIO 14,15 moved from MIO to PL Added 47 µF capacitor for SD Card VCC (required by SD spec) Added 47 µF capacitor for RPi camera - prevent voltage drop at camera init Fixed MODE pin strapping LED change 0603 Added POWER connector 2 pin Change HDMI ESD to ESD+EMI Fixed HDMI HPD and backpower DSI find solution for LS mode Fixed XADC power caps Changed LPDRR2 to DDR3L	-	TE0726-02
-	01	Inital board release	-	-

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

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Date

Revision

Contributor

Description

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

Page info

infoType	Current version
prefix	v.
type	Flat
showVersions	false

Page info

infoType	Modified by
type	Flat
showVersions	false

Removed editing bar from 2 pictures

2024-04-16

v.54

John Hartfiel

Updated to new TRM style.
Updated to board REV04.

2017-11-10

v.52

...

2017-05-24

...

V1

...

Jan Kumann

...

Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

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Trenz Electronic Documentation

Page History

Versions Compared

Old Version 52

New Version 55

Key

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Camera Serial Interface (CSI-2)

Display Serial Interface (DSI)

HDMI Interface

Audio Output

SD Card Socket

FPGA IO Banks Pin Mapping

Header J8 Interface Mapping

Default MIO Mapping

On-board LEDs

On-board Peripherals

System Controller CPLD

Quad SPI Flash Memory

DDR3L SDRAM

Clocking

Hi-speed USB 2.0 and 10/100 Mbit Ethernet

USB to JTAG/UART

4-Channel I2C Multiplexer

Boot Process

Power and Power-On Sequence

Power Consumption

Power Distribution Dependencies

Power Rails and Bank Voltages

Variants Currently in Production

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Weight

Revision History

Hardware Revision History

Document Change History

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Test Points

On-board Peripherals

DDR3L RAM

System Controller CPLD

USB-PHY

USB Ethernet Hub

FTDI

I²C Expander

I²C Interrupts

Oscillator

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

Recommended Power up Sequencing

Technical Specifications

Absolute Maximum Ratings *)

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents

Absolute Maximum Ratings ^*)