Page History

--  - Boot mode configuration via mdio interface (phytool)

--  - Reseting the FPGA after boot mode configuration

--  - Matched to FSBL code to show all informations while booting in linux console. For example Boot mode, pudc state ...

--  - Monitoring CR4[15:8] and CR5[10] continuously, to implement a state machine for boot mode configuration correctly.

--  - Using CR4[15:12] as control bit to reset FPGA

--  - Using CR4[9:8] as boot mode configuration , if the FPGA is not restarted still via soft reset.

--  - Using CR5[9:8] asd boot mode configuration, if the FPGA is restarted already via soft reset.

--  - Using CR[10] to monitor , if the FPGA is restarted already via soft reset.

--  - Using i2c_slave.vhd instead of I2C_to_GPIO.v