This document will be continuously updated until all 4x5 modules have been revised.
Last change:
| Company | Trenz Electronic GmbH |
|---|---|
| PCN Number | AVN-20211224 |
| Title | AVN-20211224 4 x 5 modules controller IOs redefinition |
| Subject | Information about 4x5 module controller IO rework |
| Issue Date | 20211224 |
Products Affected
This change affects all Trenz Electronic 4 x 5 SOM and Carriers*.
Affected Product | Effected Changes | Status | CPLD | Change Log current development state | Link to current firmware description |
|---|---|---|---|---|---|
| TEM0007 | #? | Unprocessed | LCMXO2-256HC | currently not available | |
| TE0710 | #? | Unprocessed | LCMXO2-256HC | TE0710 CPLD | |
| TE0711 | #? | Unprocessed | LCMXO2-256HC | TE0711 CPLD | |
| TE0712 | #? | Processing | LCMXO2-256HC | TE0712 CPLD | |
| TE0713 | #? | Unprocessed | LCMXO2-256HC | TE0713 CPLD | |
| TE0715 | #? | Processing | LCMXO2-256HC | TE0715 CPLD | |
| TE0720 | #2,#5,#6,#7 (#4 since CPLD Rev06) | Test phase | LCMXO2-1200HC | -- - Boot mode configuration via mdio interface (phytool) -- - Reseting the FPGA after boot mode configuration -- - Matched to FSBL code to show all informations while booting in linux console. For example Boot mode, pudc state ... -- - Monitoring CR4[15:8] and CR5[10] continuously, to implement a state machine for boot mode configuration correctly. -- - Using CR4[15:12] as control bit to reset FPGA -- - Using CR4[9:8] as boot mode configuration , if the FPGA is not restarted still via soft reset. -- - Using CR5[9:8] asd boot mode configuration, if the FPGA is restarted already via soft reset. -- - Using CR[10] to monitor , if the FPGA is restarted already via soft reset. -- - Using i2c_slave.vhd instead of I2C_to_GPIO.v | TE0720 CPLD |
| TE0741 | #? | Unprocessed | LCMXO2-256HC | TE0741 CPLD | |
| TE0820 | #? | Processing | LCMXO2-256HC | TE0820 CPLD | |
| TE0821 | #? | Unprocessed | LCMXO2-256HC | TE0821 CPLD | |
| TE0823 | #? | Unprocessed | LCMXO2-256HC | TE0823 CPLD | |
| TE0841 | #? | Unprocessed | LCMXO2-256HC | TE0841 CPLD | |
| TE0701 | #? | Test phase | LCMXO2-1200HC | TE0701 CPLD | |
| TE0703 | #? | Unprocessed | LCMXO2-1200HC | TE0703 CPLD - CC703S | |
| TE0705 | #? | Test phase | LCMXO2-1200HC | TE0705 CPLD | |
| TE0706 | #? | HW changes | --- | --- | --- |
| TEBA0841 | #? | HW changes | --- | --- | --- |
| TEF1002 | #? | Unprocessed | 10M08 | TEF1002 SC CPLD MAX10 | |
| TEB0707 | #? | Unprocessed | 10M08 | TEB0707 MAX10 CPLD |
Status:
- No changes: ---
- HW changes: HW changes are need to support new features
- Unprocessed: Revision not started
- Processing: Revision in process
- Test phase: rework finished test phase started
- Released (date): Firmware is released and will be used
Changes
#1
Type: Unification of the IO types
Reason: Add possibility for Zynq modules to change boot
Impact: Depends custom carrier realisation. Mostly none.
Standardization:
| Name | Module B2B Pin | Carrier B2B Pin | Direction | Changes |
|---|---|---|---|---|
| JTAGSEL | JM1-89 | JB1-90 | in | None |
| SC_EN1 | JM1-28 | JB1-27 | in | None |
| SC_NOSEQ | JM1-7 | JB1-8 | inout | Depending on module from input or not used to inout. Activate weak Pullup on CPLD, in case it's connected to CPLD Used as Multifunction Pin, in case it's connected to CPLD |
| SC_PGOOD | JM1-30 | JB1-29 | inout | depending on module from output or not used to inout with weak pullup on module Activate weak Pullup on CPLD, in case it's connected to CPLD Used as additional Boot Mode Pin on Zynq Modules |
| SC_BOOTMODE | JM1-32 | JB1-31 | in | None |
See also 4 x 5 SoM Integration Guide#4x5SoMIntegrationGuide-4x5ModuleControllerIOs
#2
Type: Redefinition of SC_PGOOD
Reason: Add possibility for Zynq modules to change boot to support QSPI Programming with newer Vivado Version.
Impact: None.
#3
Type: Redefinition of SC_NOSEQ
Reason: Add possibility for to used this pin as multifunction pin. Options depends on the module
Impact: None, as long as this pin was used as module input or bidirectional signal
#4
Type: Add JTAG timing constrains
Reason: Add timing constrain to JTAG signal to improve signal quality
Impact: None.
#5
Type: Additional features
Reason: Add possibility to identify CPLD Firmware
Impact: None.
#6
Type: Additional features
Reason: Add new module depended features to the CPLD functionality, see CPLD description
Impact: None.
#7
Type: Bugfix
Reason: Fixed some insignificant bugs,see CPLD description
Impact: None.
Method of Identification
Depending on Module series, new feature to read CPLD Firmware version was added.
Production Shipment Schedule
From XXXXX, after old stock is gone. If the new revision is not suitable for your application and still the former revision of the board is needed, please contact us.
Contact Information
If you have any questions related to this PCN, please contact Trenz Electronics Technical Support at
- forum.trenz-electronic.de
- wiki.trenz-electronic.de
- support%trenz-electronic.de (subject = PCN-JJJJMMDD)
phone
national calls: 05741 3200-0
international calls: 0049 5741 3200-0
Disclaimer
Any projected dates in this PCN are based on the most current product information at the time this PCN is being issued, but they may change due to unforeseen circumstances. For the latest schedule and any other information, please contact your local Trenz Electronic sales office, technical support or local distributor.
This PCN follows JEDEC Standard J-STD-046.
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