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Tickets:

  • Jira
    serverTrenz Electronic Bug Tracker
    serverId3f9be3c6-98ab-3688-81dd-29c959fdb2ac
    keyGT-1989
  • Jira
    serverTrenz Electronic Bug Tracker
    serverId3f9be3c6-98ab-3688-81dd-29c959fdb2ac
    keyGT-1844
  • Jira
    serverTrenz Electronic Bug Tracker
    serverId3f9be3c6-98ab-3688-81dd-29c959fdb2ac
    keyGT-1882
  • ...

...

CompanyTrenz Electronic GmbH
PCN AVN NumberAVN-20220506
TitleAVN-20220506 4 x 5 modules controller IOs redefinition
SubjectInformation about  about 4 x 5 module controller IO rework
Issue Date202205062022-05-06

Products Affected

This change affects all Trenz Electronic 4 x 5 SOM and Carriers*.

...

Affected Product

Effected ChangesStatus*CPLDChange Log current development stateLink to current firmware description
TEM0007#?UnprocessedLCMXO2-256HC
currently not available
TE0710#?UnprocessedLCMXO2-256HC
TE0710 CPLD
TE0711#?UnprocessedLCMXO2-256HC
TE0711 CPLD
TE0712#3,#4,#5,#6Test phaseLCMXO2-256HC

  • Renaming the port signals according to the schematic.

  • Defining and reading CPLD Revision via i2c I2C interface.

  • JTAG signal timing adjustment

  • Adding i2c I2C to gpio ip (i2c_slave.vhd)

  • LED function was changed.

TE0712 CPLD
TE0713#?UnprocessedLCMXO2-256HC
TE0713 CPLD
TE0715#1,#2,#3,#4,#5,#6Test phaseLCMXO2-256HC

  • Adding boot mode configuration via hardware (dip switch) and firmware (cpldCPLD)

  • PGOOD pin is used as boot mode selector pin.

  • Pullup or pulldown states of PORT pins was checked.

  • Adding i2c I2C to gpio ip (i2c_slave.vhd)

  • Changing oscillator frequency from 12.09 MHZ to 24.18MHZ

  • PORT signals according to the schematic are renamed.

  • JTAG time constraint correcture

  • Adding boot mode the option configuration via linux console 

TE0715 CPLD
TE0720#1,#2,#5,#6,#7
(#4 since CPLD Rev06)		Test phaseLCMXO2-1200HC
  • Boot mode configuration via mdio interface (phytool)
  • PGOOD pin is used as boot mode selector pin.
  • Reseting the FPGA after boot mode configuration
  • Matched to FSBL code to show all informations while booting in linux console. For example Boot mode, pudc state ...
  • Monitoring CR4[15:8] and CR5[10] continuously, to implement a state machine for boot mode configuration correctly.
  • Using CR4[15:12] as control bit to reset FPGA
  • Using CR4[9:8] as boot mode configuration , if the FPGA is not restarted still via soft reset.
  • Defining a new input register for mdio_slave_interface (CR5)
  • Using CR5[9:8] as boot mode configuration, if the FPGA is restarted already via soft reset.
  • Using CR[10] to monitor , if the FPGA is restarted already via soft reset.
  • Using i2c_slave.vhd instead of I2C_to_GPIO.v      
  • Changing firmware register MDIO_SL_REGISTER_4_CONTENT to CPLD_REVISION register 
TE0720 CPLD
TE0741#?UnprocessedLCMXO2-256HC
TE0741 CPLD
TE0820#1,#2,#3,#4,#5,#6ProcessingLCMXO2-256HC

  • Adding configuration of boot mode in linux console and via generic parameters

  • PGOOD pin used as boot mode selector pin.

  • Adding boot mode configuration via hardware

  • JTAG time constraint correcture

  • Adding i2c I2C to gpio ip (i2c_slave.vhd)

  • LED function was changed.

TE0820 CPLD
TE0821#1,#2,#3,#4,#5,#6ProcessingLCMXO2-256HC

  • Adding configuration of boot mode in linux console and via generic parameters

  • PGOOD pin used as boot mode selector pin.

  • Adding boot mode configuration via hardware

  • JTAG time constraint correcture

  • Adding i2c I2C to gpio ip (i2c_slave.vhd)

  • LED function was changed.

TE0821 CPLD
TE0823#1,#2,#3,#4,#5,#6ProcessingLCMXO2-256HC

  • Adding configuration of boot mode in linux console and via generic parameters

  • PGOOD pin used as boot mode selector pin.

  • Adding boot mode configuration via hardware

  • JTAG time constraint correcture

  • Adding i2c I2C to gpio ip (i2c_slave.vhd)

  • LED function was changed.

TE0823 CPLD
TE0841#?UnprocessedLCMXO2-256HC
TE0841 CPLD
TE0701#2, #4Test phaseLCMXO2-1200HC
  • Connecting PGOOD to CM2 to use as boot mode pin selector
  • JTAG timing correction
TE0701 CPLD
TE0703#?UnprocessedLCMXO2-1200HC
TE0703 CPLD - CC703S
TE0705#2, #3, #4Test phaseLCMXO2-1200HC

  • Access to CPLD chip of TE0715

  • USR0 is used as PGOOD, if Access_to_TE0715_CPLD is activated.

  • USR1 is used as JTAGMODE signal of TE0715 CPLD chip. USR1 = ON --> Access to FPGA , USR1 = OFF --> Access to CPLD

  • USR2 is used as selector signal to access to TE0715 CPLD , if Access_to_TE0715_CPLD variable is 2.

  • JTAG Timing correction

TE0705 CPLD
TE0706#?HW changes---------
TEBA0841#?HW changes---------
TEF1002#?Unprocessed10M08
TEF1002 SC CPLD MAX10
TEB0707#?Unprocessed10M08
TEB0707 MAX10 CPLD

*Status:

  • No changes: ---
  • HW changes: HW changes are need to support new features
  • Unprocessed: Revision not started
  • Processing: Revision in process
  • Test phase:  rework finished test phase started
  • Released (date): Firmware is released and will be used

Changes

#1

...

Unification of the IO types

Type: Improvement

Reason: Add possibility for Zynq modules to change boot

...

 See also 4 x 5 SoM Integration Guide#4x5SoMIntegrationGuide-4x5ModuleControllerIOs

#2

...

Redefinition of SC_PGOOD

Type: Improvement

Reason: Add possibility for Zynq modules to support more boot modes (mostly QSPI, SD, JTAG). JTAG only boot mode is needed for QSPI Programming with newer Vivado Version. See AR#00002 - QSPI Programming issues

Impact: None.

#3

...

Redefinition of SC_NOSEQ

Type:Improvement

Reason: Add possibility for to used this pin as multifunction pin. Options depends on the module

Impact: None, as long as this pin was used as module input or bidirectional signal

#4

...

Add JTAG timing constrains

Type: Improvement

Reason: Add timing constrain to JTAG signal to improve signal quality

Impact: None.

#5 CPLD Firmware Identification

Type: CPLD Firmware IdentificationImprovement

Reason: Add possibility to identify CPLD Firmware via FPGA. Interface depends on module (I2C, MDIO,...)

Impact: None.

#6 Additional features

Type: Additional featuresImprovement

Reason: Add new module depended features to the CPLD functionality, see CPLD description

Impact: None.

#7 Bugfix

Type: Bugfix

Reason: Fixed some insignificant bugs, see CPLD description

...

Contact Information

If you have any questions related to this PCNAVN, please contact Trenz Electronics Technical Support at

Disclaimer

Any projected dates in this PCN AVN are based on the most current product information at the time this PCN AVN is being issued, but they may change due to unforeseen circumstances.  For the latest schedule and any other information, please contact your local Trenz Electronic sales office, technical support or local distributor.

This PCN AVN follows JEDEC Standard JStandard J-STD-046.