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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Overview
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Refer to http://trenz.org/te0763-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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Release Notes and Know Issues
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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*used as reference |
Design supports following carriers:
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*used as reference |
Additional HW Requirements:
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*used as reference |
Content
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For general structure and usage of the reference design, see Project Delivery - Xilinx devices
Design Sources
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Additional Sources
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Prebuilt
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Download
Reference Design is only usable with the specified Vivado/Vitis version. Do never use different Versions of Xilinx Software for the same project.
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Reference Design for download is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- Xilinx
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Create Bitstream and hardware description file (.xsa file) and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Info Using Vivado GUI to generate the Bitstream is the same, except file export to prebuilt folder.
Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Launch
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for hello_te0763.mcs on QSPI Flash.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp hello_te0763
Note To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
- Set Boot Mode to QSPI-Boot.
- Depends on Carrier, see carrier TRM.
JTAG
- Connect JTAG and power on PCB
- Open Vivado HW Manager
- Program FPGA with Bitfile from "prebuilt\hardware\<short dir>\"
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select QSPI Boot Mode
Info Note: See TRM of the Carrier, which is used.
Tip Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scrJTAG Console:
- Connect the Platform Cable and Launch XSCT or the XSDB console:
- type: connect
- type: targets -set -filter {name =~ "MicroBlaze Debug*"} -index 0
- type: jtagterminal -start
- Terminal starts printing out "Hello Trenz Module" in a loop:
Expand title boot process 1. FPGA loads Bitstream(hello_te0763 application included) from Flash
2. The hello_te0763.elf application starts
2. Hello Trenz will be run on JTAG console
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP???
1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze with Linux
1. FPGA Loads Bitfile from Flash,
2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)
3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),
4. U-boot loads Linux from QSPI Flash into DDR
for native FPGA
...
- Connect the Platform Cable and Launch XSCT or the XSDB console:
Vivado HW Manager
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Set radix from VIO signals (clk_2, clk_0, fpga_24MHz, SYSCLK_100MHz) to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz - Monitoring: Four Clocks, status and various reset signals and
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System Design - Vivado
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Block Design
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Constraints
Basic module constraints
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
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set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] # # # |
Design specific constraints
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#CLKS set_property PACKAGE_PIN Y18 [get_ports {FPGA_24MHz[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_24MHz[0]}] set_property PACKAGE_PIN C18 [get_ports {SYSCLK[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {SYSCLK[0]}] |
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## Clock signal create_clock -period 41.666 -name {CLK1B[0]} -waveform {0.000 20.833} [get_ports {FPGA_24MHz[0]}] create_clock -period 10.000 -name {CLK1B[0]} -waveform {0.000 5.000} [get_ports {SYSCLK[0]}] |
Software Design - Vitis
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For Vitis project creation, follow instructions from:
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2021.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2021.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2021.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2021.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2021.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2021.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
Hello TE0763
Trenz Hello World example as endless loop instead of one console output.
Template location: \sw_lib\sw_apps\hello_te0763
Additional Software
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Cypress USB Controller
Software and Firmware modified to work with TE0763
Link to TE-USB-Suite-Master
App. A: Change History and Legal Notices
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
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Legal Notices
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