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Template Revision 2.0 - on construction2

TRM Name always "TE Series Name" +TRM, for example, "TE0720 TRM"


HTML
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  width: 100% !important;
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add a note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:

        Create DrawIO object here: Attention if you copy from other page, use
        Scroll Title
        anchorFigure_x
        titleFigure x: Text
        Scroll Ignore


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until a scroll pdf export bug is fixed


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from another page, use



      • Table template:

        • Layout macro can be use used for a landscape of large tables
        • Set column width manually(can be used for small tables to fit over the whole page) or leave empty (automatically)


      • Scroll Title
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        titleTable x: Text

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        ExampleComment
        12
  • ...
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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

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    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
  • ...


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Table of Contents

Table of Contents

Overview

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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:

  • Link to the base folder of the module (remove de/ or en/ from the URL): for example https://shop

Notes :


Scroll Ignore

Download PDF version of this document.


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Table of Contents

Table of Contents

Overview

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Notes :

The Trenz Electronic TEC0850 board is a CompactPCI Serial card (3U form factor) integrating a Xilinx Zynq UltraScale+ MPSoC, one DDR4 SDRAM SODIMM socket with 64bit wide databusdata bus, max. dual 512 MByte Flash memory for configuration and operation, 24 Gigabit transceivers on PL side and 4 on PS side, powerful switch-mode power supplies for all on-board onboard voltages, USB2 and USB3 FIFO bridges and a large number of configurable I/Os available on the CompactPCI Serial backplane connectors.

Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.

...

  • Zynq UltraScale+ MPSoC ZU15

  • Front side interface connectors
    • RJ-45 GbE Ethernet interface
    • Circular push/pull connector with 4x on-board 8bit DAC output
    • MicroSD Card connector
    • USB2 and USB3 USB 2.0 and USB 3.0 to FIFO bridge connector
    • 4x status LEDs
  • 4 CompactPCI Serial connectors for backplane connection (3U form factor)
    • 24 GTH lanes
    • 4 PS GTR lanes
    • USB2 USB 2.0 interface
    • 64 Zynq PL HP I/O's
    • 8x PLL clock input
    • JTAG, I²C and 7 user I/O's to MAX10 FPGA

  • 64bit DDR4 SODIMM (PS connected), 8 GByte maximum

  • Dual parallel QSPI Flash (bootable), 512 MByte maximum

  • 26-pin header with 20 Zynq PL HD I/O's
  • 3-pin header with 2 MAX10 FPGA I/O's
  • System Controller (Altera MAX10 FPGA SoC)
    • Power Sequencing
    • System management and control for MPSoC and on-board onboard peripherals
  • Si5345 programmable 10 output PLL clock generator
  • Si53340 Quad clock buffer
  • 2x 4bit DIP switches
  • 1x user push button
  • Zynq MPSoC cooling FAN connector
  • On-board high-efficiency DC-DC converters

...

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titleFigure 1: TEC0850-02 block diagram


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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below

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titleFigure 2: TEC0850-02 main components


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  1. GbE RJ-45 MagJack, J7
  2. 5-pin circular push/pull receptacle connector for DAC output, J15
  3. Micro USB2 USB 2.0 B receptacle connector, J9
  4. MicroSD Card socket, J11
  5. USB 3.0 Type C connector, J10
  6. LED light pipes J14 integrating LEDs D1 ... D4
  7. 4bit DIP-switch, S2
  8. 4bit DIP-switch, S1
  9. FTDI FT2232 USB2 to FIFO USB 2.0 to UART/JTAG bridge, U4
  10. 3-pin PicoBlade header, J8
  11. MAX10 FPGA JTAG/UART 10-pin header, J13
  12. Altera MAX10 System Controller FPGA, U18
  13. 4-Wire PWM fan connector, J17
  14. 26-pin IDC header for FPGA PL I/O's, J16
  15. DDR4 SO-DIMM 260-pin socket, U3
  16. Battery Holder CR1220, B1
  17. 256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U24
  18. 256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U25
  19. DC-DC Converter LT8471IFE @+5VA/-5VA, U74
  20. DC-DC Converter EM2130L02QI @VCCINT_0V85, U17
  21. DC-DC Converter 171050601 @5V, U50
  22. Xilinx Zynq Ultrascale+ MPSoC, U1
  23. Si5345A 10-output I²C programmable PLL clock, U14
  24. Main power fuse @2.5A/16V, F1
  25. cPCI connector, J1
  26. cPCI connector, J4
  27. cPCI connector, J5
  28. cPCI connector, J6
  29. FTDI FT601Q USB3 USB 3.0 to FIFO bridge, U9
  30. TI THS5641 8bit DAC ,U28
  31. TI THS5641 8bit DAC ,U31
  32. TI THS5641 8bit DAC ,U29
  33. TI THS5641 8bit DAC ,U33
  34. Marvell Alaska 88E1512 GbE PHY ,U20

Initial Delivery State

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titleTable 1: Initial delivery state of programmable devices on the module.

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Storage device name

Content

Notes

User configuration EEPROMs (1x Microchip 24AA128T-I/ST, 1x Microchip 24AA025E48T-I/OT)EmptyNot programmed
USB2 to FIFO USB 2.0 to UART/JTAG bridge configuration EEPROM (ST M93C66)EmptyNot programmed
Si5345A programmable PLL NVM OTPEmptyNot programmed
2x QSPI Flash memoryEmptyNot programmed


...

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  • Overview of Boot Mode, Reset, Enables,

Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector typ (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

CompactPCI Backplane Connectors

The TEC0850 board is equipped with 3 CompactPCI high speed backplane connectors which provides serial high-speed interconnects with transmission rates up to 12 Gb/s to the Zynq MPSoCs MGT lanes, high speed USB2 interface and single ended FPGA I/O pins Zynq MPSoC and the System Controller FPGA.

The connectors support single ended and differential signaling as the Zynq MPSoC FPGA I/O's are routed from the FPGA banks as LVDS-pairs to the backplane connector.

The TEC0850 board is designed to be connected to the System Slot of the backplane connector, whereby 4 of the 6 connectors of the System Slot configuration are fitted to the TEC0850 board.

Following diagram gives an overview of the CompactPCI backplane connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller FPGA U18:

...

anchorFigure_3
titleFigure 3: TEC0850-02 CompactPCI I/O and high-speed interfaces

To get started with TEC0850 board, some initial signals should be set described in the following table:

Scroll Title
anchorTable_OV_CS
titleTEC0850 Control Signals

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Control signal

Switch / ButtonSignal Schematic Names

Connected to

Functionality

Notes
SC JTAGENS1-1JTAGENSC FPGA U18, bank 1B, pin E5OFF: MAX 10 JTAG enabled,
ON: Zynq MPSoC JTAG enabled		-
EEPROM WPS1-2WPEEPROM U63, pin 7Write protect, active on OFF position-
FPGA PUDCS1-3PUDC_BZynq MPSOC PS Config Bank 503, pin AD15ON: internal pull-up resistors enabled, OFF: floating-
SC SwitchS1-4SW4SC FPGA U18, bank 8, pin A5low active logicReserved for future use
4bit boot mode setting codeS2-1MODE3Zynq MPSOC PS Config Bank 503, pin R23Set 4-bit code for boot mode selection,
most common modes are as follows:

Set DIP-switches as bit pattern
"S1-4 | S1-3 | S1-2 | S1-1  :  Mode":

ON | ON | ON  | ON   :  JTAG Boot
ON | ON | ON  | OFF  :  Quad-SPI
ON | ON | OFF | OFF  :  SD Card

See Zynq UltraScale+ Device Technical Reference Manual
page 236 for full boot modes description

S2-2MODE2Zynq MPSOC PS Config Bank 503, pin T23
S2-3MODE1Zynq MPSOC PS Config Bank 503, pin R22
S2-4MODE0Zynq MPSOC PS Config Bank 503, pin T22
Push buttonS3USR_BTNSC FPGA U18, bank 5, pin J10low active logicSee the documentation of the firmware of SC FPGA
U18 for current functionality of the onboard Push Button S3
SC FPGA U18 Resetheader J13, pin 6M10_RSTSC FPGA U18, bank 8, pin A7low active reset line-


Signals, Interfaces, and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on a description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which need carrier us only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

CompactPCI Serial Backplane Connectors

The TEC0850 board is equipped with 3 CompactPCI  Serial high-speed backplane connectors which provide serial high-speed interconnects with transmission rates up to 12 Gb/s to the Zynq MPSoCs MGT lanes. On the cPCI connectors are also available single-ended Zynq MPSoC PL HP I/O's, high-speed USB 2.0 interface and single-ended I/O's of the System Controller FPGA.

The connectors support single-ended and differential signaling to the Zynq MPSoC PL HP banks 65 and 66 as those FPGA I/O's are routed as LVDS-pairs to the backplane connector.

The TEC0850 board is designed to be connected to the System Slot of the backplane, whereby 4 of the 6 connectors of the System Slot configuration are fitted to the TEC0850 board.

Following diagram gives an overview of the CompactPCI Serial backplane connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller FPGA U18:

Scroll Title
anchorFigure_SIP_CompactPCI
titleTEC0850-02 CompactPCI I/O and high-speed interfaces


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Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the cPCI connectors:

  1. CompactPCI Serial Connector J1
  2. CompactPCI Serial Connector J3
  3. CompactPCI Serial Connector J4
  4. CompactPCI Serial Connector J5
  5. CompactPCI Serial Connector J6



Anchor
CompactPCI Connector J1
CompactPCI Connector J1

CompactPCI Serial Connector J1


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titlecPCI J1 interfaces

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InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
I/O1-SC FPGA U18 Bank 6+3V_Dcontrol signals in cPCI pin assignment
6-SC FPGA U18 Bank 8+3V_Dcontrol signals in cPCI pin assignment
I²C2-SC FPGA U18 Bank 1A+3V_DSC FPGA U18 I²C interface
JTAG4-SC FPGA U18 Bank 1A+3V_DSC FPGA U18 JTAG interface
MGT-8 (4 x RX/TX)Bank 502 PS GTR-4x PS GTR lanes
USB2-1 (RX/TX)USB2 PHY U11-USB2 OTG A-Device (host)
Clock Input-1Clock Driver U73-1x Reference clock input from PLL clock U14




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anchorTable_SIP_cPCI_J1_mgt
titlecPCI J1 MGT lanes

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Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the cPCI connectors:

  1. CompactPCI Connector J1
  2. CompactPCI Connector J4
  3. CompactPCI Connector J5
  4. CompactPCI Connector J6

...

CompactPCI Connector J1

cPCI backplane
Scroll Title
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titleTable 2: cPCI J1 interfaces
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InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
I/O1-SC FPGA U18 Bank 6+3V_Dcontrol signals in cPCI pin assingment
6-SC FPGA U18 Bank 8+3V_Dcontrol signals in cPCI pin assingment
I²C2-SC FPGA U18 Bank 1A+3V_DSC FPGA U18 I²C interface
JTAG4-SC FPGA U18 Bank 1A+3V_DSC FPGA U18 JTAG interface
MGT-8 (4 x RX/TX)Bank 502 PS GTR-4x PS GTR lanes
USB2-1 (RX/TX)USB2 PHY U11-USB2 OTG A-Device (host)
Clock Input-1Clock Driver U73-1x Reference clock input from PLL clock U14
Scroll Title
anchorTable_3
titleTable 3: cPCI J1 MGT lanes
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MGT LaneBankTypeSignal Schematic NamecPCI Connector PinFPGA Pin
0505GTR
  • PE1_RX0_P
  • PE1_RX0_N
  • PE1_TX0_P
  • PE1_TX0_N

J1-D5
J1-E5
J1-A5
J1-B5

PS_MGTRRXP0_505, AB29
PS_MGTRRXN0_505, AB30
PS_MGTRTXP0_505, AB33
PS_MGTRTXN0_505, AB34

1505GTR
  • PE1_RX1_P
  • PE1_RX1_N
  • PE1_TX1_P
  • PE1_TX1_N

J1-J5
J1-K5
J1-G5
J1-H5

PS_MGTRRXP1_505, Y29
PS_MGTRRXN1_505, Y30
PS_MGTRTXP1_505, AA31
PS_MGTRTXN1_505, AA32

2505GTR
  • PE1_RX2_P
  • PE1_RX2_N
  • PE1_TX2_P
  • PE1_TX2_N

J1-E6
J1-F6
J1-B6
J1-C6

PS_MGTRRXP2_505, W31
PS_MGTRRXN2_505, W32
PS_MGTRTXP2_505, Y33
PS_MGTRTXN2_505, Y34

3505GTR
  • PE1_RX3_P
  • PE1_RX3_N
  • PE1_TX3_P
  • PE1_TX3_N

J1-K6
J1-L6
J1-H6
J1-I6

PS_MGTRRXP3_505, V29
PS_MGTRRXN3_505, V30
PS_MGTRTXP3_505, V33
PS_MGTRTXN3_505, V34

Scroll Title
anchorTable_4
titleTable 4: cPCI J1 clock signals

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MGT LaneBankTypeClock Signal Schematic NamecPCI Connector PinHeader J13 PinSC FPGA U18 PinNotes
  • SATA_SL
  • SATA_SCL

J1-K3
J1-J3

J13-5
J13-1

Bank 1B, Pin G1
Bank 1B, Pin G2

Supplied by 10-output PLL clock U14,

cPCI connector J1 clock signal from PLL U14 is
also shared with SC FPGA and header J13

Scroll Title
anchorTable_5
titleTable 5: cPCI J1 VCC/VCCIO
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Available VCC/VCCIOcPCI Connector PinSourceNotes
VIN_12V

J1-A1
J1-D1
J1-E1
J1-G1
J1-H1
J1-J1
J1-K1

min. cur.: 6.65A

...

CompactPCI Connector J4

...

anchorTable_6
titleTable 6: cPCI J4 MGT lanes

...

  • PE3_RX0_P
  • PE3_RX0_N
  • PE3_TX0_P
  • PE3_TX0_N

...

J4-D1
J4-E1
J4-A1
J4-B1

...

MGTHRXP0_128, T33
MGTHRXN0_128, T34
MGTHTXP0_128, T29
MGTHTXN0_128, T30

...

  • PE3_RX1_P
  • PE3_RX1_N
  • PE3_TX1_P
  • PE3_TX1_N

...

J4-J1
J4-K1
J4-G1
J4-H1

...

MGTHRXP1_128, P33
MGTHRXN1_128, P34
MGTHTXP1_128, R31
MGTHTXN1_128, R32

...

  • PE3_RX2_P
  • PE3_RX2_N
  • PE3_TX2_P
  • PE3_TX2_N

...

J4-E2
J4-F2
J4-B2
J4-C2

...

MGTHRXP2_128, N31
MGTHRXN2_128, N32
MGTHTXP2_128, P29
MGTHTXN2_128, P30

...

  • PE3_RX3_P
  • PE3_RX3_N
  • PE3_TX3_P
  • PE3_TX3_N

...

J4-K2
J4-L2
J4-H2
J4-I2

...

MGTHRXP3_128, M33
MGTHRXN3_128, M34
MGTHTXP3_128, M29
MGTHTXN3_128, M30

...

  • PE4_RX0_P
  • PE4_RX0_N
  • PE4_TX0_P
  • PE4_TX0_N

...

J4-D3
J4-E3
J4-A3
J4-B3

...

MGTHRXP0_129, L31
MGTHRXN0_129, L32
MGTHTXP0_129, K29
MGTHTXN0_129, K30

...

  • PE4_RX1_P
  • PE4_RX1_N
  • PE4_TX1_P
  • PE4_TX1_N

...

J4-J3
J4-K3
J4-G3
J4-H3

...

MGTHRXP1_129, K33
MGTHRXN1_129, K34
MGTHTXP1_129, J31
MGTHTXN1_129, J32

...

  • PE4_RX2_P
  • PE4_RX2_N
  • PE4_TX2_P
  • PE4_TX2_N

...

J4-E4
J4-F4
J4-B4
J4-C4

...

MGTHRXP2_129, H33
MGTHRXN2_129, H34
MGTHTXP2_129, H29
MGTHTXN2_129, H30

...

  • PE4_RX3_P
  • PE4_RX3_N
  • PE4_TX3_P
  • PE4_TX3_N

...

J4-K4
J4-L4
J4-H4
J4-I4

...

MGTHRXP3_129, F33
MGTHRXN3_129, F34
MGTHTXP3_129, G31
MGTHTXN3_129, G32

...

  • PE5_RX0_P
  • PE5_RX0_N
  • PE5_TX0_P
  • PE5_TX0_N

...

J4-D5
J4-E5
J4-A5
J4-B5

...

MGTHRXP3_130, B33
MGTHRXN3_130, B34
MGTHTXP3_130, A31
MGTHTXN3_130, A32

...

  • PE5_RX1_P
  • PE5_RX1_N
  • PE5_TX1_P
  • PE5_TX1_N

...

J4-J5
J4-K5
J4-G5
J4-H5

...

MGTHRXP2_130, C31
MGTHRXN2_130, C32
MGTHTXP2_130, B29
MGTHTXN2_130, B30

...

  • PE5_RX2_P
  • PE5_RX2_N
  • PE5_TX2_P
  • PE5_TX2_N

...

J4-E6
J4-F6
J4-B6
J4-C6

...

MGTHRXP1_130, D33
MGTHRXN1_130, D34
MGTHTXP1_130, D29
MGTHTXN1_130, D30

...

  • PE5_RX3_P
  • PE5_RX3_N
  • PE5_TX3_P
  • PE5_TX3_N

...

J4-K6
J4-L6
J4-H6
J4-I6

...

MGTHRXP0_130, E31
MGTHRXN0_130, E32
MGTHTXP0_130, F29
MGTHTXN0_130, F30

...

  • PE6_RX0_P
  • PE6_RX0_N
  • PE6_TX0_P
  • PE6_TX0_N

...

J4-D7
J4-E7
J4-A7
J4-B7

...

MGTHRXP3_230, A4
MGTHRXN3_230, A3
MGTHTXP3_230, A8
MGTHTXN3_230, A7

...

  • PE6_RX1_P
  • PE6_RX1_N
  • PE6_TX1_P
  • PE6_TX1_N

...

J4-J7
J4-K7
J4-G7
J4-H7

...

MGTHRXP2_230, B2
MGTHRXN2_230, B1
MGTHTXP2_230, B6
MGTHTXN2_230, B5

...

  • PE6_RX2_P
  • PE6_RX2_N
  • PE6_TX2_P
  • PE6_TX2_N

...

J4-E8
J4-F8
J4-B8
J4-C8

...

MGTHRXP1_230, C4
MGTHRXN1_230, C3
MGTHTXP1_230, D6
MGTHTXN1_230, D5

...

  • PE6_RX3_P
  • PE6_RX3_N
  • PE6_TX3_P
  • PE6_TX3_N

...

J4-K8
J4-L8
J4-H8
J4-I8

...

MGTHRXP0_230, D2
MGTHRXN0_230, D1
MGTHTXP0_230, E4
MGTHTXN0_230, E3

...

CompactPCI Connector J5

...

anchorTable_7
titleTable 7: cPCI J5 MGT lanes

...

  • PE8_RX0_P
  • PE8_RX0_N
  • PE8_TX0_P
  • PE8_TX0_N

...

J5-D3
J5-E3
J5-A3
J5-B3

...

MGTHRXP0_228, T2
MGTHRXN0_228, T1
MGTHTXP0_228, R4
MGTHTXN0_228, R3

...

  • PE8_RX1_P
  • PE8_RX1_N
  • PE8_TX1_P
  • PE8_TX1_N

...

J5-J3
J5-K3
J5-G3
J5-H3

...

MGTHRXP1_228, P2
MGTHRXN1_228, P1
MGTHTXP1_228, P6
MGTHTXN1_228, P5

...

  • PE8_RX2_P
  • PE8_RX2_N
  • PE8_TX2_P
  • PE8_TX2_N

...

J5-E4
J5-F4
J5-B4
J5-C4

...

MGTHRXP2_228, M2
MGTHRXN2_228, M1
MGTHTXP2_228, N4
MGTHTXN2_228, N3

...

  • PE8_RX3_P
  • PE8_RX3_N
  • PE8_TX3_P
  • PE8_TX3_N

...

J5-K4
J5-L4
J5-H4
J5-I4

...

MGTHRXP3_228, L4
MGTHRXN3_228, L3
MGTHTXP3_228, M6
MGTHTXN3_228, M5

...

  • PE7_RX0_P
  • PE7_RX0_N
  • PE7_TX0_P
  • PE7_TX0_N

...

J5-D1
J5-E1
J5-A1
J5-B1

...

MGTHRXP0_229, K2
MGTHRXN0_229, K1
MGTHTXP0_229, K6
MGTHTXN0_229, K5

...

  • PE7_RX1_P
  • PE7_RX1_N
  • PE7_TX1_P
  • PE7_TX1_N

...

J5-J1
J5-K1
J5-G1
J5-H1

...

MGTHRXP1_229, J4
MGTHRXN1_229, J3
MGTHTXP1_229, H6
MGTHTXN1_229, H5

...

  • PE7_RX2_P
  • PE7_RX2_N
  • PE7_TX2_P
  • PE7_TX2_N

...

J5-E2
J5-F2
J5-B2
J5-C2

...

MGTHRXP2_229, H2
MGTHRXN2_229, H1
MGTHTXP2_229, G4
MGTHTXN2_229, G3

...

  • PE7_RX3_P
  • PE7_RX3_N
  • PE7_TX3_P
  • PE7_TX3_N

...

J5-K2
J5-L2
J5-H2
J5-I2

...

MGTHRXP3_229, F2
MGTHRXN3_229, F1
MGTHTXP3_229, F6
MGTHTXN3_229, F5

FPGA Pin
0505GTR
  • PE1_RX0_P
  • PE1_RX0_N
  • PE1_TX0_P
  • PE1_TX0_N

J1-D5
J1-E5
J1-A5
J1-B5

PS_MGTRRXP0_505, AB29
PS_MGTRRXN0_505, AB30
PS_MGTRTXP0_505, AB33
PS_MGTRTXN0_505, AB34

1505GTR
  • PE1_RX1_P
  • PE1_RX1_N
  • PE1_TX1_P
  • PE1_TX1_N

J1-J5
J1-K5
J1-G5
J1-H5

PS_MGTRRXP1_505, Y29
PS_MGTRRXN1_505, Y30
PS_MGTRTXP1_505, AA31
PS_MGTRTXN1_505, AA32

2505GTR
  • PE1_RX2_P
  • PE1_RX2_N
  • PE1_TX2_P
  • PE1_TX2_N

J1-E6
J1-F6
J1-B6
J1-C6

PS_MGTRRXP2_505, W31
PS_MGTRRXN2_505, W32
PS_MGTRTXP2_505, Y33
PS_MGTRTXN2_505, Y34

3505GTR
  • PE1_RX3_P
  • PE1_RX3_N
  • PE1_TX3_P
  • PE1_TX3_N

J1-K6
J1-L6
J1-H6
J1-I6

PS_MGTRRXP3_505, V29
PS_MGTRRXN3_505, V30
PS_MGTRTXP3_505, V33
PS_MGTRTXN3_505, V34




Scroll Title
anchorTable_SIP_cPCI_J1_sata
titlecPCI J1 clock signals

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Clock Signal Schematic NamecPCI Connector PinHeader J13 PinSC FPGA U18 PinNotes
  • SATA_SL
  • SATA_SCL

J1-K3
J1-J3

J13-5
J13-1

Bank 1B, Pin G1
Bank 1B, Pin G2

Supplied by 10-output PLL clock U14,
optional if decoupling capacitors and resistors
are fitted (see schematic),
also shared with SC FPGA and header J13.




Anchor
CompactPCI Connector J3
CompactPCI Connector J3

CompactPCI Serial Connector J3

CompactPCI Serial connector J3 is not fitted on the TEC0850 board by default, but is necessary if the second optional USB2 PHY U13 if fitted and its USB2 differential serial data interface is connected to the cPCI connector J2. 


Scroll Title
anchorTable_SIP_cPCI_J3_io
titlecPCI J3 interfaces

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InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
USB2-1 (RX/TX)USB2 PHY U13-USB2 OTG A-Device (host)




Anchor
CompactPCI Connector J4
CompactPCI Connector J4

CompactPCI Serial Connector J4


Scroll Title
anchorTable_SIP_cPCI_J4_mgt
titlecPCI J4 MGT lanes

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MGT LaneBankTypeSignal Schematic NamecPCI Connector PinFPGA Pin
0128GTH
  • PE3_RX0_P
  • PE3_RX0_N
  • PE3_TX0_P
  • PE3_TX0_N

J4-D1
J4-E1
J4-A1
J4-B1

MGTHRXP0_128, T33
MGTHRXN0_128, T34
MGTHTXP0_128, T29
MGTHTXN0_128, T30

1128GTH
  • PE3_RX1_P
  • PE3_RX1_N
  • PE3_TX1_P
  • PE3_TX1_N

J4-J1
J4-K1
J4-G1
J4-H1

MGTHRXP1_128, P33
MGTHRXN1_128, P34
MGTHTXP1_128, R31
MGTHTXN1_128, R32

2128GTH
  • PE3_RX2_P
  • PE3_RX2_N
  • PE3_TX2_P
  • PE3_TX2_N

J4-E2
J4-F2
J4-B2
J4-C2

MGTHRXP2_128, N31
MGTHRXN2_128, N32
MGTHTXP2_128, P29
MGTHTXN2_128, P30

3128GTH
  • PE3_RX3_P
  • PE3_RX3_N
  • PE3_TX3_P
  • PE3_TX3_N

J4-K2
J4-L2
J4-H2
J4-I2

MGTHRXP3_128, M33
MGTHRXN3_128, M34
MGTHTXP3_128, M29
MGTHTXN3_128, M30

0129GTH
  • PE4_RX0_P
  • PE4_RX0_N
  • PE4_TX0_P
  • PE4_TX0_N

J4-D3
J4-E3
J4-A3
J4-B3

MGTHRXP0_129, L31
MGTHRXN0_129, L32
MGTHTXP0_129, K29
MGTHTXN0_129, K30

1129GTH
  • PE4_RX1_P
  • PE4_RX1_N
  • PE4_TX1_P
  • PE4_TX1_N

J4-J3
J4-K3
J4-G3
J4-H3

MGTHRXP1_129, K33
MGTHRXN1_129, K34
MGTHTXP1_129, J31
MGTHTXN1_129, J32

2129GTH
  • PE4_RX2_P
  • PE4_RX2_N
  • PE4_TX2_P
  • PE4_TX2_N

J4-E4
J4-F4
J4-B4
J4-C4

MGTHRXP2_129, H33
MGTHRXN2_129, H34
MGTHTXP2_129, H29
MGTHTXN2_129, H30

3129GTH
  • PE4_RX3_P
  • PE4_RX3_N
  • PE4_TX3_P
  • PE4_TX3_N

J4-K4
J4-L4
J4-H4
J4-I4

MGTHRXP3_129, F33
MGTHRXN3_129, F34
MGTHTXP3_129, G31
MGTHTXN3_129, G32

0130GTH
  • PE5_RX0_P
  • PE5_RX0_N
  • PE5_TX0_P
  • PE5_TX0_N

J4-D5
J4-E5
J4-A5
J4-B5

MGTHRXP3_130, B33
MGTHRXN3_130, B34
MGTHTXP3_130, A31
MGTHTXN3_130, A32

1130GTH
  • PE5_RX1_P
  • PE5_RX1_N
  • PE5_TX1_P
  • PE5_TX1_N

J4-J5
J4-K5
J4-G5
J4-H5

MGTHRXP2_130, C31
MGTHRXN2_130, C32
MGTHTXP2_130, B29
MGTHTXN2_130, B30

2130GTH
  • PE5_RX2_P
  • PE5_RX2_N
  • PE5_TX2_P
  • PE5_TX2_N

J4-E6
J4-F6
J4-B6
J4-C6

MGTHRXP1_130, D33
MGTHRXN1_130, D34
MGTHTXP1_130, D29
MGTHTXN1_130, D30

3130GTH
  • PE5_RX3_P
  • PE5_RX3_N
  • PE5_TX3_P
  • PE5_TX3_N

J4-K6
J4-L6
J4-H6
J4-I6

MGTHRXP0_130, E31
MGTHRXN0_130, E32
MGTHTXP0_130, F29
MGTHTXN0_130, F30

0230GTH
  • PE6_RX0_P
  • PE6_RX0_N
  • PE6_TX0_P
  • PE6_TX0_N

J4-D7
J4-E7
J4-A7
J4-B7

MGTHRXP3_230, A4
MGTHRXN3_230, A3
MGTHTXP3_230, A8
MGTHTXN3_230, A7

1230GTH
  • PE6_RX1_P
  • PE6_RX1_N
  • PE6_TX1_P
  • PE6_TX1_N

J4-J7
J4-K7
J4-G7
J4-H7

MGTHRXP2_230, B2
MGTHRXN2_230, B1
MGTHTXP2_230, B6
MGTHTXN2_230, B5

2230GTH
  • PE6_RX2_P
  • PE6_RX2_N
  • PE6_TX2_P
  • PE6_TX2_N

J4-E8
J4-F8
J4-B8
J4-C8

MGTHRXP1_230, C4
MGTHRXN1_230, C3
MGTHTXP1_230, D6
MGTHTXN1_230, D5

3230GTH
  • PE6_RX3_P
  • PE6_RX3_N
  • PE6_TX3_P
  • PE6_TX3_N

J4-K8
J4-L8
J4-H8
J4-I8

MGTHRXP0_230, D2
MGTHRXN0_230, D1
MGTHTXP0_230, E4
MGTHTXN0_230, E3




Anchor
CompactPCI Connector J5
CompactPCI Connector J5

CompactPCI Serial Connector J5


Scroll Title
anchorTable_SIP_cPCI_J5_mgt
titlecPCI J5 MGT lanes

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MGT LaneBankTypeSignal Schematic NamecPCI Connector PinFPGA Pin
0228GTH
  • PE8_RX0_P
  • PE8_RX0_N
  • PE8_TX0_P
  • PE8_TX0_N

J5-D3
J5-E3
J5-A3
J5-B3

MGTHRXP0_228, T2
MGTHRXN0_228, T1
MGTHTXP0_228, R4
MGTHTXN0_228, R3

1228GTH
  • PE8_RX1_P
  • PE8_RX1_N
  • PE8_TX1_P
  • PE8_TX1_N

J5-J3
J5-K3
J5-G3
J5-H3

MGTHRXP1_228, P2
MGTHRXN1_228, P1
MGTHTXP1_228, P6
MGTHTXN1_228, P5

2228GTH
  • PE8_RX2_P
  • PE8_RX2_N
  • PE8_TX2_P
  • PE8_TX2_N

J5-E4
J5-F4
J5-B4
J5-C4

MGTHRXP2_228, M2
MGTHRXN2_228, M1
MGTHTXP2_228, N4
MGTHTXN2_228, N3

3228GTH
  • PE8_RX3_P
  • PE8_RX3_N
  • PE8_TX3_P
  • PE8_TX3_N

J5-K4
J5-L4
J5-H4
J5-I4

MGTHRXP3_228, L4
MGTHRXN3_228, L3
MGTHTXP3_228, M6
MGTHTXN3_228, M5

0229GTH
  • PE7_RX0_P
  • PE7_RX0_N
  • PE7_TX0_P
  • PE7_TX0_N

J5-D1
J5-E1
J5-A1
J5-B1

MGTHRXP0_229, K2
MGTHRXN0_229, K1
MGTHTXP0_229, K6
MGTHTXN0_229, K5

1229GTH
  • PE7_RX1_P
  • PE7_RX1_N
  • PE7_TX1_P
  • PE7_TX1_N

J5-J1
J5-K1
J5-G1
J5-H1

MGTHRXP1_229, J4
MGTHRXN1_229, J3
MGTHTXP1_229, H6
MGTHTXN1_229, H5

2229GTH
  • PE7_RX2_P
  • PE7_RX2_N
  • PE7_TX2_P
  • PE7_TX2_N

J5-E2
J5-F2
J5-B2
J5-C2

MGTHRXP2_229, H2
MGTHRXN2_229, H1
MGTHTXP2_229, G4
MGTHTXN2_229, G3

3229GTH
  • PE7_RX3_P
  • PE7_RX3_N
  • PE7_TX3_P
  • PE7_TX3_N

J5-K2
J5-L2
J5-H2
J5-I2

MGTHRXP3_229, F2
MGTHRXN3_229, F1
MGTHTXP3_229, F6
MGTHTXN3_229, F5




Scroll Title
anchorTable_SIP_cPCI_J5_clock
titlecPCI J5 clock signals

...

anchorTable_8
titleTable 8: cPCI J5 clock signals:

...

  • PE1_CLK_P
  • PE1_CLK_N

...

J5-A5
J5-B5

...

reference clock signals supplied
by on-board 10-output
PLL clock generator U14

...

  • PE2_CLK_P
  • PE2_CLK_N

...

J5-D5
J5-E5

...

  • PE3_CLK_P
  • PE3_CLK_N

...

J5-G5
J5-H5

...

  • PE4_CLK_P
  • PE4_CLK_N

...

J5-J5
J5-K5

...

  • PE5_CLK_P
  • PE5_CLK_N

...

J5-B6
J5-C6

...

  • PE6_CLK_P
  • PE6_CLK_N

...

J5-E6
J5-F6

...

  • PE7_CLK_P
  • PE7_CLK_N

...

J5-H6
J5-I6

...

  • PE8_CLK_P
  • PE8_CLK_N

...

J5-K6
J5-L6

...

CompactPCI Connector J6

Scroll Title
anchorTable_9
titleTable 9: cPCI J6 Interfaces

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InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
I/O4623PL bank 66PL_1.8V-
189PL bank 65PL_1.8V-
2-SC FPGA U18 Bank 1B+3V_DSignalname: 'DET_RIO', 'DET_BPR'

USB-C Connector

Front panel USB-C Interface is connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.

...

anchorFigure_4
titleFigure 4: TEC0850-02 USB3 to FIFO bridge
PLL Clock U14 OutputSignal Schematic NamecPCI Connector J5 PinNotes
OUT1
  • PE1_CLK_P
  • PE1_CLK_N

J5-A5
J5-B5

reference clock signals supplied
by on-board 10-output
PLL clock generator U14

OUT2
  • PE2_CLK_P
  • PE2_CLK_N

J5-D5
J5-E5

OUT3
  • PE3_CLK_P
  • PE3_CLK_N

J5-G5
J5-H5

OUT4
  • PE4_CLK_P
  • PE4_CLK_N

J5-J5
J5-K5

OUT5
  • PE5_CLK_P
  • PE5_CLK_N

J5-B6
J5-C6

OUT6
  • PE6_CLK_P
  • PE6_CLK_N

J5-E6
J5-F6

OUT7
  • PE7_CLK_P
  • PE7_CLK_N

J5-H6
J5-I6

OUT8
  • PE8_CLK_P
  • PE8_CLK_N

J5-K6
J5-L6




Anchor
CompactPCI Connector J6
CompactPCI Connector J6

CompactPCI Serial Connector J6


Scroll Title
anchorTable_SIP_cPCI_J6_io
titlecPCI J6 Interfaces

...

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The USB3 to FIFO bridge FTDI FT601Q U9 is connected to the Zynq MPSoC's PL bank 64 and is accessible through USB-C connector J10:

Scroll Title
anchorTable_10
titleTable 10: USB-C connector J10

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InterfaceSignal Schematic Names
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
USB3 data lane
  • SSRX_P
  • SSRX_N
  • SSTXX_P
  • SSTXX_N

USB C Connector J10

-
USB2 data lane
  • SS_D_P
  • SS_D_N

USB C Connector J10

-
Control Lines
  • FTDI_RESET_N
  • WAKEUP_N
  • SIWU_N
  • TXE_N
  • RXF_N
  • WR_N
  • RD_N
  • OE_N
  • BE_0
  • BE_1
  • BE_2
  • BE_3
  • FIFO_CLK

PL bank 64

-
Parallel GPIO's
  • DATA0
  • .
  • .
  • DATA31
PL bank 64

32bit FIFO register

See FT600Q-FT601Q IC Datasheet for interface details.

Micro-USB2 Connector

Front panel Micro-USB2 Interface provides access to UART and JTAG functions via FTDI FT2232 chip. Use of this feature requires that USB driver is installed on your host PC. UART0 with MIO 22 .. 23 should be selected in "Zynq UltraScale+ MPSoC" configuration.

The Digilent plug-in software and cable drivers must be installed on your machine for you to be able to use JTAG interface.

I/O4623PL bank 66PL_1.8V-
189PL bank 65PL_1.8V-
2-SC FPGA U18 Bank 1B+3V_DSignalname: 'DET_RIO', 'DET_BPR'



USB-C Connector

Front panel USB-C Interface is connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.

Scroll Title
anchorFigure_SIP_usb3
titleTEC0850-02 USB3 to FIFO bridge


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anchorFigure_5
titleFigure 5: JTAG/UART Interface
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The USB2 The USB 3.0 to FIFO bridge FTDI FT2232H U4 FT601Q U9 is connected to the SC FPGA U18 Zynq MPSoC's PL bank 64 and is accessible through MicroUSB-USB2 C connector J9J10:

Scroll Title
anchorTable_11_SIP_j10_usb-c
titleTable 11: Micro-USB2 connector J9USB-C connector J10

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InterfaceSignal Schematic NamesConnected toNotes
USB2 data USB3 data lane
  • SSRX_P
  • SSRX_N
  • SSTXXUSB_P
  • USBSSTXX_N

Micro-USB2 connector J9USB C Connector J10

-
Control Lines
  • FTDI_RST

SC FPGA U18, bank 6

-
Parallel GPIO's
  • ADBUS0
  • ADBUS1
  • ADBUS2
  • ADBUS3
  • BDBUS0
  • BDBUS1
  • BDBUS2
  • BDBUS3
  • BDBUS4
  • BDBUS5
  • BDBUS6
  • BDBUS7
  • BCBUS0
  • BCBUS1
  • BCBUS2
  • BCBUS3
  • BCBUS4
SC FPGA U18, bank 6

-

SD

USB2 data lane
  • SS_D_P
  • SS_D_N

USB C Connector J10

-
Control Lines
  • FTDI_RESET_N
  • WAKEUP_N
  • SIWU_N
  • TXE_N
  • RXF_N
  • WR_N
  • RD_N
  • OE_N
  • BE_0
  • BE_1
  • BE_2
  • BE_3
  • FIFO_CLK

PL bank 64

-
Parallel GPIO's
  • DATA0
  • .
  • .
  • DATA31
PL bank 64

32bit FIFO register


See FT600Q-FT601Q IC Datasheet for interface details.

Micro-USB2 Connector

Front panel Micro-USB2 Interface provides access to UART and JTAG functions via FTDI FT2232 chip. Use of this feature requires that USB driver is installed on your host PC. UART0 with MIO 22 .. 23 should be selected in "Zynq UltraScale+ MPSoC" configuration.

The Digilent plug-in software and cable drivers must be installed on your machine for you to be able to use JTAG interfaceThe SD Card interface of the TEC0850 board is not directly wired to the connector J11 pins, but through a Texas Instruments TXS02612 SD IO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and MIO-bank of the Xilinx Zynq MPSoC. The Micro SD Card has 3.3V signal voltage level, but the PS MIO-bank on the Xilinx Zynq MPSoC has VCCIO of 1.8V.

Scroll Title
Figure 6: MicroSD Card interface
anchorFigure_SIP_jtag_6uart
titleJTAG/UART Interface


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The USB2 to FIFO bridge FTDI FT2232H U4 is connected to the SC FPGA U18 and is accessible through Micro-USB2 connector J9:

only
scroll-
title

Image Removed

There are some limitations to use SD card Interface in Linux.

  • Zynq UltraScale+ SD controller is working only in the 3.3V mode as it connected to SD card socket using SD IO port expander U10 as 1.8V to 3.3V level shifter. 
  • Micro SD card socket has no "Write Protect" switch.
Tip

To force Linux driver not to use this features add following instructions to device tree file.

&sdhci1 {

no-1-8-v;
disable-wp;
};

RJ45 - Ethernet

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 501. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the GbE PHY U20 status LED output.

...

anchorFigure_7
titleFigure 7: Gigabit Ethernet Interface
anchorTable_SIP_micro_usb2
titleMicro-USB2 connector J9

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InterfaceSignal Schematic NamesConnected toNotes
USB2 data lane
  • USB_P
  • USB_N

Micro-USB2 connector J9

-
Control Lines
  • FTDI_RST

SC FPGA U18, bank 6

-
Parallel GPIO's
  • ADBUS0
  • ADBUS1
  • ADBUS2
  • ADBUS3
  • BDBUS0
  • BDBUS1
  • BDBUS2
  • BDBUS3
  • BDBUS4
  • BDBUS5
  • BDBUS6
  • BDBUS7
  • BCBUS0
  • BCBUS1
  • BCBUS2
  • BCBUS3
  • BCBUS4
SC FPGA U18, bank 6

-


SD

The SD Card interface of the TEC0850 board is not directly wired to the connector J11 pins but through a Texas Instruments TXS02612 SD IO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and MIO-bank of the Xilinx Zynq MPSoC. The Micro SD Card has 3.3V signal voltage level, but the PS MIO-bank on the Xilinx Zynq MPSoC has VCCIO of 1.8V

...

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DDR4 SODIMM Socket

On the TEC0850 board there is a DDR4 memory interface U3 with a 64-bit databus width available for SO-DIMM modules connected to the Zynq UltraScale+ DDRC hard memory controller.

Scroll Title
Figure 8: DDR4 SDRAM SODIMM socket
anchorFigure_SIP_8microsd
titleMicroSD Card interface


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...



There are some limitations to use SD card Interface in Linux.

  • Zynq UltraScale+ SD controller is working only in the 3.3V mode as it connected to SD card socket using SD IO port expander U10 as 1.8V to 3.3V level shifter. 
  • Micro SD card socket has no "Write Protect" switch.
Tip

To force Linux driver not to use these features to add following instructions to device tree file.

&sdhci1 {

no-1-8-v;
disable-wp;
};

RJ45 - Ethernet

Onboard Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 501. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the GbE PHY U20 status LED output.

Scroll Title
anchorFigure_SIP_eth
titleGigabit Ethernet Interface


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DDR4 SODIMM Socket

On the TEC0850 board, there is a DDR4 memory interface U3 with a 64-bit data bus width available for SO-DIMM modules connected to the Zynq UltraScale+ DDRC hard memory controller.

Scroll Title
anchorFigure_SIP_ddr4
titleDDR4 SDRAM SODIMM socket


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Following table gives an overview of the memory interface I/O signals of the DDR4 SDRAM SO-DIMM Socket U3:

Scroll Title
anchorTable_SIP_ddr4
titleDDR4 SDRAM SO-DIMM socket U3

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DDR4 SDRAM I/O Signal

Signal Schematic Name

Connected toNotes
Address inputs
  • DDR4-A0 ... DDR4-A16
PS DDR Bank 504-
Bank address inputs
  • DDR4-BA0 / DDR4-BA1
-
Bank group inputs
  • DDR4-BG0 / DDR4-BG1
-
Differential clocks
  • DDR4-CLK0_P
  • DDR4-CLK0_N
  • DDR4-CLK1_P
  • DDR4-CLK1_N
2 x DDR4 clock
Data input/output
  • DQ0 ... DQ63
-
Check bit input/output
  • CB0 ... CB7
-
Data strobe (differential)
  • DDR4-DQS0_P
  • DDR4-DQS0_N
  • ...
  • DDR4-DQS8_P
  • DDR4-DQS8_N
-
Data mask and data bus inversion
  • DDR4-DM0 ... DDR4-DM8
-
Serial address inputs
  • DDR4-SA0 ...  DDR4-SA2

address range configuration on I²C bus

Control Signals
  • DDR4-CS_N0 / DDR4-CS_N1
chip select signal
  • DDR4-ODT0 / DDR4-ODT1
On-die termination enable
  • DDR4-RESET
nRESET
  • DDR4-PAR
Command and address parity input
  • DDR4-CKE0 / DDR4-CKE1
Clock Enable
  • DDR4-ALERT
CRC error flag
  • DDR4-ACT
Activation command input
  • DDR4-EVENT
Temperature event
I²C
  • DDR4-SCL
  • DDR4-SDA
not connected-


Circular Push Pull Connector

The TEC0850 board provides 4x DAC analog voltage output on the 5-pin circular push/pull connector J15. Each of the DAC units consists of one Texas Instruments THS5641AIPW digital to analog converter, TI THS4631D operational amplifier and two LDOs, by which the DAC unit can be switched on and off.

The TI THS4631D digital to analog converter wired to the operational amplifier circuitry creating the DAC unit with a voltage output range from -0.5V ... 0.5V. See TI THS5641 datasheet and schematic how to control the DAC unit and to set the analog output voltages on connector J15.   

Scroll Title
anchorFigure_SIP_dac
title4x 8bit DAC units


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Image Added

...

anchorTable_12
titleTable 12: DDR4 SDRAM SO-DIMM socket U3

...

Signal Schematic Name

...

  • DDR4-A0 ... DDR4-A16

...

  • DDR4-BA0 / DDR4-BA1

...

  • DDR4-BG0 / DDR4-BG1

...

  • DDR4-CLK0_P
  • DDR4-CLK0_N
  • DDR4-CLK1_P
  • DDR4-CLK1_N

...

  • DQ0 ... DQ63

...

  • CB0 ... CB7

...

  • DDR4-DQS0_P
  • DDR4-DQS0_N
  • ...
  • DDR4-DQS8_P
  • DDR4-DQS8_N

...

  • DDR4-DM0 ... DDR4-DM8

...

  • DDR4-SA0 ...  DDR4-SA2

...

address range configuration on I²C bus

...

  • DDR4-CS_N0 / DDR4-CS_N1

...

  • DDR4-ODT0 / DDR4-ODT1

...

  • DDR4-RESET

...

  • DDR4-PAR

...

  • DDR4-CKE0 / DDR4-CKE1

...

  • DDR4-ALERT

...

  • DDR4-ACT

...

  • DDR4-EVENT

...

  • DDR4-SCL
  • DDR4-SDA

...

Circular Push Pull Connector

The TEC0850 board provides 4x DAC analog voltage output on the 5-pin circular push/pull connector J15. Each of the DAC units consists of one Texas Instruments THS5641AIPW digital to analog converter, TI THS4631D operational amplifier and two LDOs, by which the DAC unit can be switched on and off.

The TI THS4631D digital to analog converter wired to the operational amplifier circuitry creating the DAC unit with a voltage output range from -0.5V ... 0.5V. See TI THS5641 datasheet and schematic how to control the DAC unit and to set the analog output voltages on connector J15.   

...

anchorFigure_9
titleFigure 9: 4x 8bit DAC units

...

26-Pin IDC Header

There is a 26-pin IDC header (2x13, 1.27mm grid size) J16 available on the TEC0850 board which exposes the 20 FPGA HD I/O's of PL bank 47 to the user. The PL bank 47 has 3.3V VCCO bank voltage, on the header J16 there also the voltage levels 3.3V and 5V available. The I/O's can be accessed with a corresponding IDC connector.   

...

anchorFigure_10
titleFigure 10: Zynq MPSoC PL I/O's IDC pin-header

...

10-Pin Header

On the TEC0850 there is a 10-pin SMT header (2x5, 2.54mm grid size) J13 present which provides access to the JTAG and UART interface of Altera MAX10 System Controller FPGA. The header J13 has a compatible pin assignment to the TEI0004 JTAG programmer for Altera FPGAs, the voltage levels 3.3V is on the header available as reference I/O-voltage for JTAG and UART.

The 4 JTAG pins of the header J13 are also connected to the cPCI connector J1 and can be used es user GPIO's of the SC FPGA U18 with othr functionalities then JTAG.

On the header J13 there is also a reference clock signal from PLL clcok U14 available, which can be also used for the SC FPGA U18 and on the cPCI connector J1.

Figure 11: 10-pin JTAG/UART header
Scroll Title
anchorFigure_11
title


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...


26-Pin

...

IDC Header

There is a 26-pin IDC header (2x13, 1.27mm grid size) J16 available on the TEC0850 board which exposes the 20 FPGA HD 2 I/O's of the SC FPGA U18 are exposed to the on-board 3-Pin PicoBlade header J8 available to the user or for future use of upcoming versions of SC FPGA firmware.PL bank 47 to the user. The PL bank 47 has 3.3V VCCO bank voltage, on the header J16 there also the voltage levels 3.3V and 5V available. The I/O's can be accessed with a corresponding IDC connector.   

Scroll Title
Figure 12: 3-pin PicoBlade header
anchorFigure_12SIP_idc_mpsoc_pl
titleZynq MPSoC PL I/O's IDC pin-header


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Battery Holder

There is a CR1220 battery holder available to the supply the voltage for the  for  for the Zynq MPSoC's Battery Power Domain (BBRAM and RTC). The battery voltage VBATT should be in the range of 2.2V to 5.5V, use 3.0V CR1220 battery.

diagramDisplayName

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anchorFigure_13
titleFigure 13: Backup-Battery Holder
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10-

...

Pin Header

On the TEC0850 there is a 10-pin SMT header (2x5, 2.54mm grid size) J13 present which provides access to the JTAG and UART interface of Altera MAX10 System Controller FPGA. The header J13 has a compatible pin assignment to the TEI0004 JTAG programmer for Altera FPGAs, the voltage levels 3.3V is on the header available as a reference I/O-voltage for JTAG and UART.

The 4 JTAG pins of the header J13 are also connected to the cPCI connector J1 and can be used as user GPIO's of the SC FPGA U18 with other functionalities then JTAG.

On the header J13, there is also a optional reference clock signal from PLL clock U14 available, if the necessary resistors and capacitors are fitted on board. The clock can also be used for the SC FPGA U18 and on the cPCI connector J1.

Scroll Title
anchorFigure_SIP_10pin_jtag_uart
title10-pin JTAG/UART header


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4-Wire PWM FAN Connectors

The TEC0850 offers one 4-wire PWM FAN connector FPGA cooling fan controlled by SC FPGA U18:

Figure 14: 4-wire PWM FAN connector
Scroll Title
anchorFigure_14
title


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3-

...

Image Removed

On-board Peripherals

Page properties
hiddentrue
idComments

Notes :

  • add subsection for every component which is important for design, for example:
    • Ethernet PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

Zynq UltraScale XCZU15EG MPSoC

The TEC0850 board is populated with the Zynq UltraScale+ XCZU15EG-1FFVB1156E MPSoC.

The PS MIO pins are routed to the on-board peripherals as follows:

...

anchorTable_13
titleTable 13: Default MIO Configuration

...

MAX10 System Controller FPGA

The TEC0850 board is equipped with one System Controller FPGA (Intel MAX10 10M08SAU169C8G) with the schematic designators U18. The  SC FPGA is the central system management unit where essential control signals are logically linked by the implemented logic in FPGA firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and UART between the FTDI FT2232H chip and to the Zynq MPSoC are by-passed, forwarded and controlled by the System Controller FPGA.

Other tasks of the System Controller FPGA are the monitoring of the power-on sequence and to display the programming state of the FPGA module. The functionalities and configuration of the pins depend on the SC FPGA's firmware. The documentation of the firmware of SC FPGA U18 contains detailed information on this matter.

The Sytem Controller FPGA is connected to the Zynq Ultrascale+ MPSoC through MIO and PL pins. The signals of these pins are forwarded by the SC FPGA to control some of the on board peripherals.

Following block diagram visualizes the connection of the SC FPGA with the Zynq Ultrascale+ MPSoC via 4 PS MIO pins (MIO22 ... 25), PS Config control signals and 10 singled ended PL HD bank 48 I/O pins (MAX_IO1 ... MAX_IO10):

...

anchorFigure_2
titleFigure 2: TEF1001-02 main components

...

Programmable Clock Generator

There is a Si5345A U14, Silicon Labs I2C programmable 10-output PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and on-board peripherals.

...

anchorFigure_2
titleFigure 2: TEF1001-02 main components

...

Following table shows on-board Silicon Labs I2C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:

...

anchorTable_x
titleTable x: SI5345 I2C address

...

  • IN0_P

...

  • IN0_N

...

-

...

-

...

not used

...

  • CLK0_P

...

reference clock input to
Quad clock buffer

...

  • CLK0_N

...

  • PE1_CLK_N

...

reference clock output
to cPCI connector J5

...

  • PE1_CLK_P

...

  • PE5_CLK_N

...

  • PE5_CLK_P

...

  • PE2_CLK_N

...

  • PE2_CLK_P

...

  • PE3_CLK_N

...

  • PE3_CLK_P

...

  • PE4_CLK_N

...

  • PE4_CLK_P

...

  • PE6_CLK_N

...

  • PE6_CLK_P

...

  • PE8_CLK_N

...

  • PE8_CLK_P

...

  • PE7_CLK_N

...

  • PE7_CLK_P

...

  • CLK9_P

...

reference clock input to
dual clock driver

...

  • CLK9_N

...

  • XAXB_P

...

  • XAXB_N

...

SCLK,
SDA/SDIO

...

  • I2C_SCL
  • I2C_SDA

...

  • MIO20
  • MIO21

...

anchorTable_x
titleTable x: SI5345 I2C address

...

  • CLK1_P
  • CLK1_N

...

U1, pin G8
U1, pin G7

...

  • CLK2_P
  • CLK2_N

...

U1, pin Y8
U1, pin Y7

...

  • CLK3_P
  • CLK3_N

...

U1, pin U27
U1, pin U28

...

  • CLK4_P
  • CLK4_N

...

U1, pin L27
U1, pin L28

...

  • CK_PLL_P
  • CK_PLL_N

...

U1, pin AG5
U1, pin AG4

...

  • CK_P
  • CK_N

...

Signal 'SATA_SL'
Signal  'SATA_SCL'

...

Pin PicoBlade Header

2 I/O's of the SC FPGA U18 are exposed to the on-board 3-Pin PicoBlade header J8 available to the user or for future use of upcoming versions of SC FPGA firmware.

Scroll Title
anchorFigure_SIP_3pin_picoblade
title3-pin PicoBlade header


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Battery Holder

There is a CR1220 battery holder available to the supply the voltage for the Zynq MPSoC's Battery Power Domain (BBRAM and RTC). The battery voltage VBATT should be in the range of 2.2V to 5.5V, use the 3.0V CR1220 battery.

Scroll Title
anchorFigure_SIP_Battery_Holder
titleBackup-Battery Holder


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4-Wire PWM FAN Connectors

The TEC0850 offers one 4-wire PWM FAN connector FPGA cooling fan controlled by SC FPGA U18:

Scroll Title
anchorFigure_SIP_fan
title4-wire PWM FAN connector


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Onboard Peripherals

Page properties
hiddentrue
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Notes :

  • add a subsection for every component which is important for design, for example:
    • Ethernet PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

Zynq UltraScale XCZU15EG MPSoC

The TEC0850 board is populated with the Zynq UltraScale+ XCZU15EG-1FFVB1156E MPSoC.

The PS MIO pins are routed to the onboard peripherals as follows:

Scroll Title
anchorTable_OBP_default_mio
titleDefault MIO Configuration

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PS MIOFunctionConnected to
0QSPI*U24-B2, CLK
1QSPI*U24-D2, DO/IO1
2QSPI*U24-C4, WP/IO2
3QSPI*U24-D4, HOLD/IO3
4QSPI*U24-D3, DI/IO0 
5QSPI* U24-C2, CS
6-not connected
7QSPI*U25-C2, CS
8QSPI*U25-D3, DI/IO0
9QSPI*U25-D2, DO/IO1
10QSPI*U17-C4, WP/IO2
11QSPI*U25-D4, HOLD/IO3
12QSPI*U25-B2, CLK
13 ... 15-not connected
16USB2 PHY ResetUSB2 PHY U11, pin27
17USB2 PHY ResetUSB2 PHY U13, pin27 (optional, PHY not fitted by default)
18 ... 19-not connected
20 ...21PS MIO I²CI²C peripherals
22 ... 25user MIOSC FPGA U18, bank 2
26 ... 38RGMIIGbE PHY U20
39 ... 44-not connected
45 ... 51SD IOMicroSD Card socket J11
52 ... 63USB2 ULPIUSB2 PHY U11
64 ... 75USB2 ULPIUSB2 PHY U13 (optional, PHY not fitted by default)
76 ... 77ETH MDC / MDIOGbE PHY U20

* Flash is used as QSPI dual parallel

MAX10 System Controller FPGA

The TEC0850 board is equipped with one System Controller FPGA (Intel MAX10 10M08SAU169C8G) with the schematic designators U18. The  SC FPGA is the central system management unit where essential control signals are logically linked by the implemented logic in FPGA firmware, which generates output signals to control the system, the onboard peripherals, and the interfaces. Interfaces like JTAG and UART between the FTDI FT2232H chip and to the Zynq MPSoC are by-passed, forwarded and controlled by the System Controller FPGA.

Other tasks of the System Controller FPGA are the monitoring of the power-on sequence and to display the programming state of the FPGA module. The functionalities and configuration of the pins depending on the SC FPGA's firmware. The documentation of the firmware of SC FPGA U18 contains detailed information on this matter.

The System Controller FPGA is connected to the Zynq Ultrascale+ MPSoC through MIO and PL pins. The signals of these pins are forwarded by the SC FPGA to control some of the onboard peripherals.

Following block diagram visualizes the connection of the SC FPGA with the Zynq Ultrascale+ MPSoC via 4 PS MIO pins (MIO22 ... 25), PS Config control signals and 10 singled ended PL HD bank 48 I/O pins (MAX_IO1 ... MAX_IO10):

Scroll Title
anchorFigure_OBP_max10_sc
titleTEC0850 MAX10 System Controller FPGA


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Programmable Clock Generator

There is a Si5345A U14, Silicon Labs I2C programmable 10-output PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and onboard peripherals.

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anchorFigure_OBP_si5345
title10-output I²C programmable clock generator


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Following table shows onboard Silicon Labs I2C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:

Scroll Title
anchorTable_OBP_si5345
titleSI5345 Clock Outputs

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Si5345A U14 Pin
Signal Schematic Name
Connected toSignal DirectionNote
IN0
  • IN0_P
40.000 MHz Oscillator U75Inputexternal reference
clock input
  • IN0_N
GND
IN1-not connectedInputnot used
-not connected
IN2

-

not connectedInputnot used
-not connected
IN3

-

not connectedInput

not used

-not connected
OUT0
  • CLK0_P
Quad clock buffer
Si53340 U16		Output

reference clock input to
Quad clock buffer

  • CLK0_N
OUT1
  • PE1_CLK_N
cPCI J5, pin B5Output

reference clock output
to cPCI connector J5

  • PE1_CLK_P
cPCI J5, pin A5
OUT2
  • PE5_CLK_N
cPCI J5, pin C6Output
  • PE5_CLK_P
cPCI J5, pin B6
OUT3
  • PE2_CLK_N
cPCI J5, pin E5Output
  • PE2_CLK_P
cPCI J5, pin D5
OUT4
  • PE3_CLK_N
cPCI J5, pin H5Output
  • PE3_CLK_P
cPCI J5, pin G5
OUT5
  • PE4_CLK_N
cPCI J5, pin K5Output
  • PE4_CLK_P
cPCI J5, pin J5
OUT6
  • PE6_CLK_N
cPCI J5, pin F6Output
  • PE6_CLK_P
cPCI J5, pin E6
OUT7
  • PE8_CLK_N
cPCI J5, pin L6Output
  • PE8_CLK_P
cPCI J5, pin K6
OUT8
  • PE7_CLK_N
cPCI J5, pin I6Output
  • PE7_CLK_P
cPCI J5, pin H6
OUT9
  • CLK9_P
Clock Driver LTC6975 U73Output

reference clock input to
dual clock driver U73

  • CLK9_N
XA/XB
  • XAXB_P
54.000 MHz quartz
oscillator Y3		InputDifferential quartz oscillator
clock input
  • XAXB_N

SCLK,
SDA/SDIO

  • I2C_SCL
  • I2C_SDA
  • MIO20
  • MIO21
BiDirI²C address 0x69



The clock outputs OUT1 and OUT9 are distributed via clock buffer U16 and clock driver U14 to several PL and MGT banks:

Scroll Title
anchorTable_OBP_clk_buffer
titleClock driver and buffer outputs

The clock generator U14 is programmable via the on-board I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.

...

anchorTable_x
titleTable x: SI5345 I2C address

...

Oscillators

The TEC0850 board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:

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titleTable x: SI5345 I2C address

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Clock SourceSi53340 U16 Pin
Signal Schematic Name
Connected toFrequencyClock Input Destination
SiTime SiT8008BI oscillator, U22
  • PS_CLK
33.333333 MHzZynq MPSoC U1 PS Config Bank 503, pin U24
SiTime SiT8008AI oscillator, U12
  • USB0_CLK
52.000000 MHzUSB2 transceiver PHY U11, pin 26
SiTime SiT8008AI oscillator, U16
  • OSCI
12.000000 MHzFTDI FT2232H U4, pin 3
Kyocera CX3225SB30000, Y1-30.000 MHzFTDI FT601Q U9, pin 21/22
CM-2012-2pad, Y2-32.768000 kHzZynq MPSoC U1 PS Config Bank 503, pin V21/V22
Kyocera CX3225SB26000, Y3
  • XAXB_P
  • XAXB_N
54.000 MHz10-output PLL clock generator U14, pin 8/9
SiTime SiT8008BI oscillator, U21
  • ETH_CLKIN
25.000000 MHzGigabit Ethernet PHY U20, pin 34
ASVTX-12-A oscillator, U75
  • IN0_P
40.000 MHz10-output PLL clock generator U14, pin 63

FTDIs

The TEC0850 board is equipped with 2 FTDI chips FT2232H (U4) and FT601Q (U9). Both chips are USB to Multipurpose UART/FIFO bridges which converts signals from USB2 or USB3 to a variety of standard serial and parallel interfaces.

...

anchorFigure_11
titleFigure 11: CAN interface
Signal DirectionNote
Q0
  • CLK1_P
  • CLK1_N

U1, pin G8
U1, pin G7

OutputGTH bank 229 reference clock input
Q1
  • CLK2_P
  • CLK2_N

U1, pin Y8
U1, pin Y7

OutputPL HP bank 66 reference clock input
Q2
  • CLK3_P
  • CLK3_N

U1, pin U27
U1, pin U28

OutputPS GTR Bank 505 reference clock input
Q3
  • CLK4_P
  • CLK4_N

U1, pin L27
U1, pin L28

OutputGTH bank 129 reference clock input
LTC6957 U73 Pin



OUT1
  • CK_PLL_P
  • CK_PLL_N

U1, pin AG5
U1, pin AG4

OutputPL HP bank 65 reference clock input
OUT2
  • CK_P
  • CK_N

Signal 'SATA_SL'
Signal  'SATA_SCL'

Output

optional reference clock input to cPCI connector J1,
if decoupling capacitors and resistors
are fitted (see schematic),
also shared with SC FPGA and header J13



The clock generator U14 is programmable via the onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.

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titleSI5345 I2C address

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I2C addressChipDescription
0x69U14 Si5345Clock generator and distributor


Oscillators

The TEC0850 board is equipped several onboard oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the onboard peripherals with reference clock-signals:

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Clock SourceSignal Schematic NameFrequencyClock Input Destination
SiTime SiT8008BI oscillator, U22
  • PS_CLK
33.333333 MHzZynq MPSoC U1 PS Config Bank 503, pin U24
SiTime SiT8008AI oscillator, U12
  • USB0_CLK
52.000000 MHzUSB2 transceiver PHY U11, pin 26
SiTime SiT8008AI oscillator, U16
  • OSCI
12.000000 MHzFTDI FT2232H U4, pin 3
Kyocera CX3225SB30000, Y1-30.000 MHzFTDI FT601Q U9, pin 21/22
CM-2012-2pad, Y2-32.768000 kHzZynq MPSoC U1 PS Config Bank 503, pin V21/V22
Kyocera CX3225SB26000, Y3
  • XAXB_P
  • XAXB_N
54.000 MHz10-output PLL clock generator U14, pin 8/9
SiTime SiT8008BI oscillator, U21
  • ETH_CLKIN
25.000000 MHzGigabit Ethernet PHY U20, pin 34
ASVTX-12-A oscillator, U75
  • IN0_P
40.000 MHz10-output PLL clock generator U14, pin 63


FTDIs

The TEC0850 board is equipped with 2 FTDI chips FT2232H (U4) and FT601Q (U9). Both chips are USB to Multipurpose UART/FIFO bridges which converts signals from USB2 or USB3 to a variety of standard serial and parallel interfaces.

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titleTEC0850 on-board FTDI chips


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FT2232H

The TEC0850 board is equipped with the FTDI FT2232H USB2 to JTAG/UART adapter controller connected to micro-USB2 connector J9 to provide JTAG and UART access to the Xilinx UltraScale+ Zynq SoC or Intel MAX10 (switchable over DIP) . There is also a 256-byte configuration EEPROM U6 wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI datasheet to get information about the capacity of the FT2232H chip.

Warning

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license, the onboard JTAG will not be accessible anymore with any Xilinx tools. Software tools from the FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

Channel A of the FTDI IC is configured as JTAG interface (MPSSE) connected to the SC FPGA U18, the JTAG signals are forwarded to the JTAG interface of the Zynq MPSoC on PS config bank 503.

Channel B can be used as UART Interface routed to SC FPGA U18, 11 I/O's of Channel B is routed to are usable for example as GPIOs and other standard interfaces.

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titleFT2232H interface connections

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FT2232H U3 PinSignal Schematic NameConnected toNotes
Pin 12, ADBUS0ADBUS0SC FPGA U18 bank 6, pin G9
JTAG interface
Pin 13, ADBUS1ADBUS1SC FPGA U18 bank 6, pin F10
Pin 14, ADBUS2ADBUS2SC FPGA U18 bank 6, pin E10
Pin 15, ADBUS3ADBUS3

SC FPGA U18 bank 6, pin D9

Pin 32, BDBUS0BDBUS0SC FPGA U18 bank 6, pin B11

UART and
user configurable

GPIO's


Pin 33, BDBUS1BDBUS1SC FPGA U18 bank 6, pin A12
Pin 34, BDBUS2BDBUS2SC FPGA U18 bank 6, pin B12
Pin 35, BDBUS3BDBUS3SC FPGA U18 bank 6, pin C11
Pin 37, BDBUS4BDBUS4SC FPGA U18 bank 6, pin B13
Pin 38, BDBUS5BDBUS5SC FPGA U18 bank 6, pin C12
Pin 39, BDBUS6BDBUS6SC FPGA U18 bank 6, pin C13
Pin 40, BDBUS7BDBUS7SC FPGA U18 bank 6, pin D11
Pin 42, BCBUS0BCBUS0SC FPGA U18 bank 6, pin D12
Pin 46, BCBUS1BCBUS1SC FPGA U18 bank 6, pin E13
Pin 47, BCBUS2BCBUS2SC FPGA U18 bank 6, pin E12
Pin 48, BCBUS3BCBUS3SC FPGA U18 bank 6, pin F13
Pin 49, BCBUS4BCBUS4SC FPGA U18 bank 6, pin F12
Pin 11, nRESETFTDI_RSTSC FPGA U18 bank 6, pin E9control signals



FT601Q

The TEC0850 board is equipped with the FTDI FT601Q USB3 to 32bit-FIFO adapter controller connected to USB-C connector J10 to provide access to the Zynq MPSoC PL HP I/O's of bank 64. Also, 13 control signals of the FTDI FT601Q are connected to the HP bank 64

...

The TEC0850 board is equipped with the FTDI FT2232H USB2 to JTAG/UART adapter controller connected to micro-USB2 connector J9 to provide JTAG and UART access to the Xilinx Zynq XC7Z010 SoC. There is also a 256-byte configuration EEPROM U6 wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.

Warning

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

Channel A of the FTDI IC is configured as JTAG interface (MPSSE) connected to the SC FPGA U18, the JTAG signals are forwarded to the JTAG interface of the Zynq MPSoC on PS config bank 503.

Channel B can be used as UART Interface routed to SC FPGA U18, 11 I/O's of Channel B are routed to are usable for example as GPIOs and other standard interfaces.

Scroll Title
anchorTable_OBP_xft601q
titleTable x: SI5345 I2C addressFT601Q interface connections

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UART and
user configurable

GPIO's
FT2232H U3 FT601Q U9 PinSignal Schematic NameConnected toNotes
Pin 12, ADBUS0ADBUS0SC FPGA U18 bank 6, pin G9
JTAG interface
Pin 13, ADBUS1ADBUS1SC FPGA U18 bank 6, pin F10
Pin 14, ADBUS2ADBUS2SC FPGA U18 bank 6, pin E10
Pin 15, ADBUS3ADBUS3

SC FPGA U18 bank 6, pin D9

Pin 32, BDBUS0BDBUS0SC FPGA U18 bank 6, pin B11
Pin 33, BDBUS1BDBUS1SC FPGA U18 bank 6, pin A12
Pin 34, BDBUS2BDBUS2SC FPGA U18 bank 6, pin B12
Pin 35, BDBUS3BDBUS3SC FPGA U18 bank 6, pin C11
Pin 37, BDBUS4BDBUS4SC FPGA U18 bank 6, pin B13
Pin 38, BDBUS5BDBUS5SC FPGA U18 bank 6, pin C12
Pin 39, BDBUS6BDBUS6SC FPGA U18 bank 6, pin C13
Pin 40, BDBUS7BDBUS7SC FPGA U18 bank 6, pin D11
Pin 42, BCBUS0BCBUS0SC FPGA U18 bank 6, pin D12
Pin 46, BCBUS1BCBUS1SC FPGA U18 bank 6, pin E13
Pin 47, BCBUS2BCBUS2SC FPGA U18 bank 6, pin E12
Pin 48, BCBUS3BCBUS3SC FPGA U18 bank 6, pin F13
Pin 49, BCBUS4BCBUS4SC FPGA U18 bank 6, pin F12

...

The TEC0850 board is equipped with the FTDI FT601Q USB3 to 32bit-FIFO adapter controller connected to USB-C connector J10 to provide access to the Zynq MPSoC PL HP I/O's of bank 64. Also 13 control signals of the FTDI FT601Q are connected to the HP bank 64.

...

anchorTable_x
titleTable x: SI5345 I2C address

...

40, DATA0DATA0PL HP bank 64, pin AK1user GPIO's
Pin 41, DATA1DATA1PL HP bank 64, pin AJ10
Pin 42, DATA2DATA2PL HP bank 64, pin AJ9
Pin 43, DATA3DATA3PL HP bank 64, pin AK7
Pin 44, DATA4DATA4PL HP bank 64, pin AK5
Pin 45, DATA5DATA5PL HP bank 64, pin AM1
Pin 46, DATA6DATA6PL HP bank 64, pin AL2
Pin 47, DATA7DATA7PL HP bank 64, pin AK4
Pin 50, DATA8DATA8PL HP bank 64, pin AN1
Pin 51, DATA9DATA9PL HP bank 64, pin AL3
Pin 52, DATA10DATA10PL HP bank 64, pin AK8
Pin 53, DATA11DATA11PL HP bank 64, pin AN2
Pin 54, DATA12DATA12PL HP bank 64, pin AP2
Pin 55, DATA13DATA13PL HP bank 64, pin AL7
Pin 56, DATA14DATA14PL HP bank 64, pin AL5
Pin 57, DATA15DATA15PL HP bank 64, pin AM4
Pin 60, DATA16DATA16PL HP bank 64, pin AN4
Pin 61, DATA17DATA17PL HP bank 64, pin AM5
Pin 62, DATA18DATA18PL HP bank 64, pin AM6
Pin 63, DATA19DATA19PL HP bank 64, pin AN3
Pin 64, DATA20DATA20PL HP bank 64, pin AP3
Pin 65, DATA21DATA21PL HP bank 64, pin AP4
Pin 66, DATA22DATA22PL HP bank 64, pin AP5
Pin 67, DATA23DATA23PL HP bank 64, pin AN6
Pin 69, DATA24DATA24PL HP bank 64, pin AN7
Pin 70, DATA25DATA25PL HP bank 64, pin AP6
Pin 71, DATA26DATA26PL HP bank 64, pin AP7
Pin 72, DATA27DATA27PL HP bank 64, pin AP11
Pin 73, DATA28DATA28PL HP bank 64, pin AP10
Pin 74, DATA29DATA29PL HP bank 64, pin AP9
Pin 75, DATA30DATA30PL HP bank 64, pin AN9
Pin 76, DATA31DATA31PL HP bank 64, pin AP8
Pin 58, CLKFIFO_CLKPL HP bank 64, pin AL6control signals
Pin 4, BE0BE_0PL HP bank 64, pin AM10
Pin 5, BE1BE_1PL HP bank 64, pin AK10
Pin 6, BE2BE_2PL HP bank 64, pin AM11
Pin 7, BE3BE_3PL HP bank 64, pin AL11
Pin 13, nOEOE_NPL HP bank 64, pin AL8
Pin 12, nRDRD_NPL HP bank 64, pin AK9
Pin 11, nWRWR_NPL HP bank 64, pin AM9
Pin 8, nTXETXE_NPL HP bank 64, pin AK12
Pin 9, nRXNRXF_NPL HP bank 64, pin AJ12
Pin 10, nSIWUSIWU_NPL HP bank 64, pin AL10
Pin 15, nRESETFTDI_RESET_NPL HP bank 64, pin AM8
Pin 16, nWAKEUPWAKEUP_NPL HP bank 64, pin AN8


Quad-SPI Flash Memory

On-board QSPI flash memory U24 and U25 on the TEC0850 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each, 64 MByte total QSPI Flash memory. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC, enabling dual parallel booting from QSPI Flash memory. This nonvolatile memory is used to store an initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

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ICMemory DensityMIOSignal Schematic NameFlash Memory Pin

QSPI Flash U24,

N25Q256A11E1240E

256 Mbit (32 MByte)0

MIO0

B2
1

MIO1

D2
2

MIO2

C4
3

MIO3

D4
4

MIO4

D3
5

MIO5

C2

QSPI Flash U25,

N25Q256A11E1240

256 Mbit (32 MByte)7

MIO7

C2
8MIO8D3
9MIO9D2
10MIO10C4
11MIO11D4
12MIO12B2


EEPROMs

The TEC0850 board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip, the I²C interfaces are connected to Zynq MPSoC bank 502 MIO 20...21 pins:

Scroll Title
anchorFigure_OBP_eeprom
titleOn-board configuration EEPROMs


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Quad-SPI Flash Memory

On-board QSPI flash memory U24 and U25 on the TEC0850 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each, 64 MByte total QSPI Flash memory. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC, enabling dual parallel booting from QSPI Flash memory. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Figure 11: CAN interface
Scroll Title
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The EEPROMs U63 and U64 are programmable via the onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.

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titleTable x: SI5345 I2C addressEEPROMs I²C Addresses

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ICMemory DensityMIOSignal Schematic NameFlash Memory Pin

QSPI Flash U24,

N25Q256A11E1240E

256 Mbit (32 MByte)0

MIO0

B2
1

MIO1

D2
2

MIO2

C4
3

MIO3

D4
4

MIO4

D3
5

MIO5

C2

QSPI Flash U25,

N25Q256A11E1240

256 Mbit (32 MByte)7

MIO7

C2
8MIO8D3
9MIO9D2
10MIO10C4
11MIO11D4
12MIO12B2

EEPROMs

I2C addressChipDescription
0x50U63 24AA128T-I/ST128K Serial EEPROM
0x53U64 24AA025E48T-I/OT2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity


USB2 PHY

USB2 PHY U11 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator U12. There is also the option to equip the TEC0850 board with a second USB2 PHY U13 connected to the optional cPCI backplane connector J3. Both, the optional USB2 PHY U13 and cPCI connector J3 are not fitted by default.The TEC0850 board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip, the I²C interfaces is connected to Zynq MPSoC bank 502 MIO 20...21 pins:

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titleFigure 11: CAN interface
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The EEPROMs U63 and U64 are programmable via the on-board I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.

...

anchorTable_x
titleTable x: EEPROMs I2C Addresses

...

TEC0850 cPCI USB2 interface


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USB2 PHY U11 PinConnected toNotes
ULPIPS bank MIO52 ... MIO63Zynq Ultrascale+ USB0 MIO pins are connected to the PHY
REFCLK-52MHz from onboard oscillator U12
REFSEL[0..2]-All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETB

Zynq MPSoC MIO16, pin AM16

Low active USB2 PHY Reset
DP, DMcPCI connector J1USB2 data lane
CPEN-External USB power switch active-high enable signal
VBUS5VConnected to onboard 5V voltage level via a series of resistors, see schematic
ID3.3VUSB2 OTG A-Device (host)
optional USB2 PHY U13

USB2 PHY

USB2 PHY U15 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator U12.

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titleFigure 11: CAN interface
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USB0 on board
PHY PinConnected toNotes
ULPIPS bank MIO52 MIO64 ... MIO63MIO75Zynq Ultrascale+ USB1 MIO pins are connected to the PHY
REFCLK-52MHz from onboard oscillator U12
REFSEL[0..2]-All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETBZynq MPSoC MIO16MIO17, pin AM16AP16Low active USB2 PHY Reset
DP, DMoptional cPCI connector J1J3USB2 data lane
CPEN-External USB power switch active-high enable signal
VBUS5VConnected to USB VBUS onboard 5V voltage level via a series of resistors, see schematic
ID3.3VB-deviceUSB2 OTG A-Device (host)


Gigabit Ethernet PHY

On-board Onboard Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512, which use MDIO address 1.. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21.

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Figure 11: CAN interface
anchorFigure_11OBP_eth_phy
titleTEC0850 GbE interface with RJ-45 MegJack


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8bit DACs

The TEC0850 Board has 4 8-bit parallel  Texas Instruments THS5641AIPW digital to analog converter (DAC) with up to 100 MSPS update rate connected to TI THS4631D operational amplifiers. See Schematic circuitry and TI THS5641 data sheet for proper operation of the on-board DAC units.

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DAC unitSignal Schematic NameConnected toFunctionality

DAC1

U28

DAC1_D0

PL HD bank 50, pin D11

Digital input bits D[7:0]


D7 is the most significant data bit (MSB),
D0 is the least significant data bit (LSB).

DAC1_D1

PL HD bank 50, pin D10

DAC1_D2

PL HD bank 50, pin G11

DAC1_D3

PL HD bank 50, pin J11

DAC1_D4

PL HD bank 50, pin G10

DAC1_D5

PL HD bank 50, pin H10

DAC1_D6PL HD bank 50, pin J10
DAC1_D7PL HD bank 50, pin E10
DAC1_CLKPL HD bank 50, pin F12External clock input, input data latched on rising edge of the clock.
DAC1_MODEPL HD bank 50, pin F10Input code format (binary, twos complement)
EN_DAC1SC FPGA U18 bank 8, pinE6generate 3.3V voltages
LDO U35, U34

DAC2

U31

DAC2_D0PL HD bank 50, pin G15

Digital input bits D[7:0]


D7 is the most significant data bit (MSB),
D0 is the least significant data bit (LSB).

DAC2_D1

PL HD bank 50, pin H14

DAC2_D2

PL HD bank 50, pin J14

DAC2_D3PL HD bank 50, pin G14
DAC2_D4PL HD bank 50, pin G13
DAC2_D5PL HD bank 50, pin H13
DAC2_D6PL HD bank 50, pin H12
DAC2_D7PL HD bank 50, pin J12
DAC2_CLKPL HD bank 50, pin F12
External clock input, input data latched on rising edge of the clock.
DAC2_MODEPL HD bank 50, pin F11
Input code format (binary, twos complement)
EN_DAC2SC FPGA U18 bank 8, pin E8
generate 3.3V voltages
LDO U32, U60

DAC3

U29

DAC3_D0PL HD bank 44, pin AG14

Digital input bits D[7:0]


D7 is the most significant data bit (MSB),
D0 is the least significant data bit (LSB).

DAC3_D1PL HD bank 44, pin AE13
DAC3_D2PL HD bank 44, pin AG13
DAC3_D3PL HD bank 44, pin AJ15
DAC3_D4PL HD bank 44, pin AJ14
DAC3_D5PL HD bank 44, pin AH14
DAC3_D6PL HD bank 44, pin AL13
DAC3_D7PL HD bank 44, pin AM13
DAC3_CLKPL HD bank 44, pin AK15
External clock input, input data latched on rising edge of the clock.
DAC3_MODEPL HD bank 44, pin AK14
Input code format (binary, twos complement)
EN_DAC3SC FPGA U18 bank 8, pin B6
generate 3.3V voltages
LDO U66, U68

DAC4

U33

DAC4_D0PL HD bank 44, pin AP14

Digital input bits D[7:0]


D7 is the most significant data bit (MSB),
D0 is the least significant data bit (LSB).

DAC4_D1PL HD bank 44, pin AN14
DAC4_D2PL HD bank 44, pin AM14
DAC4_D3PL HD bank 44, pin AN13
DAC4_D4PL HD bank 44, pin AP12
DAC4_D5PL HD bank 44, pin AN12
DAC4_D6PL HD bank 44, pin AF13
DAC4_D7PL HD bank 44, pin AH13
DAC4_CLKPL HD bank 44, pin AK13
External clock input, input data latched on rising edge of the clock.
DAC4_MODEPL HD bank 44, pin AK13Input code format (binary, twos complement)
EN_DAC4SC FPGA U18 bank 8, pin A6
generate 3.3V voltages
LDO U70, U72


...

There are two 4-bit DIP-witches S3 and S4 present on the TEC0850 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

Table The table below describes the functionalities of the switches of DIP-switches S1 and S2 at their each positionsevery position:

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DIP-switch S1Signal Schematic NameConnected toFunctionalityNotes
S1-1

JTAGEN

SC FPGA U18, bank 1B, pin E5

Positions:
OFF: SC FPGA's JTAG enabled
ON: SC FPGAZynq MPSoC's JTAG disabledenabled

to switch the JTAG pins to user GPIO's if JTAG is disabledinterface between SC FPGA and Zynq MPSoC
S1-2

WP

EEPROM U63, pin 7

Positions:
OFF: Write Protect is enabled
ON: Write Protect is disabled

-
S1-3

PUDC_B

Zynq MPSOC PS Config Bank 503, pin AD15

Positions:
ON: PUDC_B is Low
OFF: PUDC_B is HIGH

Internal pull-up resistors during configuration
are enabled at ON-position, means I/O's are 3-stated
until the configuration of the FPGA completes.

S1-4

SW4

SC FPGA U18, bank 8, pin A5SC Switch (Reserved for future use)low active logic
DIP-switch S2Signal Schematic NameConnected toFunctionalityNotes
S2-1

MODE3

Zynq MPSOC PS Config Bank 503, pin R23

set 4-bit code for boot mode selection

R23

set 4-bit code for boot mode selection

See Zynq UltraScale+ Device Technical Reference Manual
page 236 for full boot modes description


Set DIP-switches as bit pattern of S2

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BOOT Mode1234
Quad-SPI (32bONONOFFON
SD1 (2.0)ONOFFONOFF
JTAGONONONON

See Zynq UltraScale+ Device Technical Reference Manual
page 236 for full boot modes description

Set DIP-switches as  bit pattern "S1-4 | S1-3 | S1-2 | S1-1  :  Boot Mode":

ON | ON | ON  | ON   :  JTAG Boot Mode
ON | ON | ON  | OFF  :  Quad-SPI
ON | ON | OFF | OFF  :  SD Card





S2-2

MODE2

Zynq MPSOC PS Config Bank 503, pin T23

S2-3

MODE1

Zynq MPSOC PS Config Bank 503, pin R22

S2-4

MODE0

Zynq MPSOC PS Config Bank 503, pin T22


...

There is one switch button available to the user connected to the SC FPGA U18:

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ButtonSignal Schematic NameConnected toNotes
S3USR_BTNS3SC FPGA U18, bank 5, pin J10

low active logic

Refer documentation of the firmware of SC FPGA U18.


...

The TEC0850 board is equipped with several LEDs to signal current states and activities.

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LEDColorConnected toDescription and Notes
Front panel LED D1RedZynq MPSoC PL bank 11, pin AF15PL User defined LED
Front panel LED D2GreenZynq MPSoC PL bank 11, pin AG15PL User defined LED
Front panel LED D3GreenZynq MPSoC PL bank 11, pin AE15PL User defined LED
Front panel LED D4GreenSC FPGA U18 bank 3, pin M4Power Good


...

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide provides a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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Power InputTypical Current
VIN_12VTBD*


Power supply with a minimum current capability of 6.65A 5A (60W@12V, CompactPCI Serial spec.) for system startup is recommended.

The TEC0850 board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet an embedded system power management requirement by advanced power management features. This These features allow to offset offsetting the power and heat constraints against overall performance and operational efficiency.

...

There are following dependencies how the initial 24V voltage from the main power pins on cPCI slot J1 is distributed to the on-board onboard DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

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Power-On Sequence

The TEC0850 board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board onboard DC-DC converters dedicated to the particular Power Domains and powering up the on-board onboard voltages.

On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller FPGA U18:

...

Hence, those three power instances will be powered up consecutively when the Power-Good signals of the previous instance is are asserted.

Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.

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Warning
To avoid any damage to the MPSoC module, check for stabilized on-board voltages in steady onboard voltages in a steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/Os should be tri-stated during the power-on sequence.

It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning that all on-board onboard voltages have become stable and the module is properly powered up.

...

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Figure 4: Power-On Sequence Diagram
anchorFigure_4PWR_PM
titleVoltage monitor circuit


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Power Rails

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Connector / PinVoltageDirectionNotes
J1, pin A1, D1, E1, G1, H1, J1, K1VIN_12VInputMain power supply pins
J17, pin 212VOutput4-wire PWM fan connector supply voltage
J13, pin 4+3V_DOutputJTAG/UART reference VCCIO voltage
B1, pin +VBATTInput3.0V CR1220 battery
J16, pin 25VOutputI/O header VCCIO
J16, pin 13.3VOutputI/O header VCCIO
J9, pin 4VBUSInputUSB2 VBUS (5.0V nominal)
J10, pin A4, B9VBUS30InputUSB3 VBUS (5.0V nominal)
J11, pin 43.3VOutputMicroSD Card VDD
J15, pin 2DAC1_OUTOutputDAC output
J15, pin 3DAC2_OUTOutputDAC output
J15, pin 4DAC3_OUTOutputDAC output
J15, pin 5DAC4_OUTOutputDAC output


Bank Voltages

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Zynq MPSoC BankTypeSchematic NameVoltageVoltage Range
44HD3.3V3.3Vfixed to 3.3V
47HD3.3V3.3Vfixed to 3.3V
48HD3.3V3.3Vfixed to 3.3V
49HD3.3V3.3Vfixed to 3.3V
50HD3.3V3.3Vfixed to 3.3V
64HPPL_1V81.8Vfixed to 1.8V
65HPPL_1V81.8Vfixed to 1.8V
66HPPL_1V81.8Vfixed to 1.8V
67HPPL_1V81.8Vfixed to 1.8V
500MIOPS_1V81.8Vfixed to 1.8V
501MIOPS_1V81.8Vfixed to 1.8V
502MIOPS_1V81.8Vfixed to 1.8V
503CONFIGPS_1V81.8Vfixed to 1.8V
504PSDDRDDR_1V2
DDR_PLL

1.2V
1.8V

fixed bank voltages

128

129

130

GTH

AVCC_L

AUX_L

AVTT_L

0.9V

1.8V

1.2V

fixed bank voltages

228

229

230

GTH

AVCC_R

AUX_R

AVTT_R

0.9V

1.8V

1.2V

fixed bank voltages
MAX10 FPGA BankTypeSchematic NameVoltageVoltage Range
1A-+3V_D3.3Vfixed to 3.3V
1B-+3V_D3.3Vfixed to 3.3V
2-PS_1V81.8Vfixed to 1.8V
3-3.3V3.3Vfixed to 3.3V
5-+3V_D3.3Vfixed to 3.3V
6-+3V_D3.3Vfixed to 3.3V
8-+3V_D3.3Vfixed to 3.3V


...

Absolute Maximum Ratings

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Parameter

MinMax

Unit

Reference Document

Notes
VIN_12V-0.316VIntel Enpirion EM2130 data sheet / Fuse F1Fuse F1 @16V/2.5A
VBATT-0.36VTPS780180300 data sheet1.8V typical output
VCCO for HD I/O banks-0.53.4VXilinx document DS925-
VCCO for HP I/O banks-0.52VXilinx document DS925-
I/O input voltage for HD I/O banks-0.55VCCO + 0.55VXilinx document DS925-
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VXilinx document DS925-
PS I/O input voltage (MIO pins)-0.5VCCO_PSIO + 0.55VXilinx document DS925VCCO_PSIO 1.8V nominally
PS GTR reference clocks absolute input voltage-0.51.1VXilinx document DS925-
PS GTR absolute input voltage-0.51.1VXilinx document DS925-
MGT clock absolute input voltage-0.51.3VXilinx document DS925-

MGT Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage

-0.51.2VXilinx document DS925-

SC FPGA U18 I/O input voltage

-0.5VCC + 0.5VIntel MAX 10 data sheetVCC 3.3V nominally
Voltage A voltage on input I/O pins of DC-DC U17 EM2130
on header J12		-0.33.6VIntel Enpirion EM2130 data sheetEM2130 datasheet-

Storage temperature (ambient)

-40

85

°C

ASVTX-12 data sheetdatasheet-


Recommended Operating Conditions

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ParameterMinMaxUnitReference DocumentNotes
VIN_12V1214VIntel Enpirion EM2130 data sheetEM2130 datasheet12V nominally input voltage, min. current 6.65A
VBATT2.25.5VTPS780180300 data sheetsupplied by 3.0V CR1220 battery
VCCO for HD I/O banks1.143.4VXilinx document DS925-
VCCO for HP I/O banks0.951.9VXilinx document DS925-
I/O input voltage for HD I/O banks-0.2VCCO + 0.2VXilinx document DS925-
I/O input voltage for HP I/O banks-0.2VCCO + 0.2VXilinx document DS925-
PS I/O input voltage (MIO pins)-0.2VCCO_PSIO + 0.2VXilinx document DS925VCCO_PSIO 1.8V nominally
SC FPGA U18 I/O input voltage0VCCV

Intel MAX 10 data sheet

VCC 3.3V nominally
Board Operating Temperature Range 1), 2)085°CXilinx document DS925extended grade Zynq MPSoC temperarure temperature range



1) Temperature range may vary depending on assembly options

2) The operating temperature range of the Zynq MPSoC, SC FPGA SoC and on-board onboard peripherals are a junction and also ambient operating temperature ranges

...

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titleFigure x: Physical dimensions drawing

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titleTable x: Shop Overview

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Trenz shop TE0xxx overview page
English pageGerman page


...

Hardware Revision History

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DateRevision

Notes

PCNDocumentation LinkNotes
-

02

current available board revision

-TEC0850-02current available board revision
-01
Prototypes
--
-
Prototypes


Document Change History

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    • Metadata is only used of for compatibility of older exports


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DateRevisionConstributorDescription

Page info
infoType

Modified date
dateFormatyyyy-MM-dd
typeFlat

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Page info
infoTypeCurrent version
prefixv.
typeFlat
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Page info
infoTypeModified by
typeFlat
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  • boot mode bugfix
2018-10-26v.103John Hartfiel
  • change" Compact PCI" to "Compact PCI Serial"

v.102Ali Naseri
  • small corrections


v.101


John Hartfiel


  • style changes

v.97Ali Naseri

  • added information about the optional second USB2 PHY and cPCI connector J2 (not fitted by default)

v.94

John Hartfiel

  • small style changes and typo correction

v.93 Ali Naseri , Oleksandr Kiyenko , John Hartfiel
  • initial release
--all

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  • --


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