If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add a note, that this part is configurable
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
<type>_<main section>_<name>
type: Figure, Table
main section:
"OV" for Overview
"SIP" for Signal Interfaces and Pins,
"OBP" for On board Peripherals,
"PWR" for Power and Power-On Sequence,
"B2B" for Board to Board Connector,
"TS" for Technical Specification
"VCP" for Variants Currently in Production
"RH" for Revision History
name: custom, some fix names, see below
Fix names:
"Figure_OV_BD" for Block Diagram
"Figure_OV_MC" for Main Components
"Table_OV_IDS" for Initial Delivery State
"Table_PWR_PC" for Power Consumption
"Figure_PWR_PD" for Power Distribution
"Figure_PWR_PS" for Power Sequence
"Figure_PWR_PM" for Power Monitoring
"Table_PWR_PR" for Power Rails
"Table_PWR_BV" for Bank Voltages
"Table_TS_AMR" for Absolute_Maximum_Ratings
"Table_TS_ROC" for Recommended_Operating_Conditions
"Figure_TS_PD" for Physical_Dimensions
"Table_VCP_SO" for TE_Shop_Overview
"Table_RH_HRH" for Hardware_Revision_History
"Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
The Trenz Electronic TEC0850 board is a CompactPCI Serial card (3U form factor) integrating a Xilinx Zynq UltraScale+ MPSoC, one DDR4 SDRAM SODIMM socket with 64bit wide databusdata bus, max. dual 512 MByte Flash memory for configuration and operation, 24 Gigabit transceivers on PL side and 4 on PS side, powerful switch-mode power supplies for all on-board onboard voltages, USB2 and USB3 FIFO bridges and a large number of configurable I/Os available on the CompactPCI Serial backplane connectors.
Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.
...
Zynq UltraScale+ MPSoC ZU15
Front side interface connectors
RJ-45 GbE Ethernet interface
Circular push/pull connector with 4x on-board 8bit DAC output
MicroSD Card connector
USB2 and USB3 USB 2.0 and USB 3.0 to FIFO bridge connector
4x status LEDs
4 CompactPCI Serial connectors for backplane connection (3U form factor)
24 GTH lanes
4 PS GTR lanes
USB2 USB 2.0 interface
64 Zynq PL HP I/O's
8x PLL clock input
JTAG, I²C and 7 user I/O's to MAX10 FPGA
64bit DDR4 SODIMM (PS connected), 8 GByte maximum
Dual parallel QSPI Flash (bootable), 512 MByte maximum
26-pin header with 20 Zynq PL HD I/O's
3-pin header with 2 MAX10 FPGA I/O's
System Controller (Altera MAX10 FPGA SoC)
Power Sequencing
System management and control for MPSoC and on-board onboard peripherals
Si5345 programmable 10 output PLL clock generator
Si53340 Quad clock buffer
2x 4bit DIP switches
1x user push button
Zynq MPSoC cooling FAN connector
On-board high-efficiency DC-DC converters
Block Diagram
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Figure 1: TEC0850-02 block diagram
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Main Components
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Notes :
Picture of the PCB (top and bottom side) with labels of important components
Add List below
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Figure 2: TEC0850-02 main components
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GbE RJ-45 MagJack, J7
5-pin circular push/pull receptacle connector for DAC output, J15
Micro USB2 USB 2.0 B receptacle connector, J9
MicroSD Card socket, J11
USB 3.0 Type C connector, J10
LED light pipes J14 integrating LEDs D1 ... D4
4bit DIP-switch, S2
4bit DIP-switch, S1
FTDI FT2232 USB2 to FIFO USB 2.0 to UART/JTAG bridge, U4
3-pin PicoBlade header, J8
MAX10 FPGA JTAG/UART 10-pin header, J13
Altera MAX10 System Controller FPGA, U18
4-Wire PWM fan connector, J17
26-pin IDC header for FPGA PL I/O's, J16
DDR4 SO-DIMM 260-pin socket, U3
Battery Holder CR1220, B1
256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U24
256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U25
DC-DC Converter LT8471IFE @+5VA/-5VA, U74
DC-DC Converter EM2130L02QI @VCCINT_0V85, U17
DC-DC Converter 171050601 @5V, U50
Xilinx Zynq Ultrascale+ MPSoC, U1
Si5345A 10-output I²C programmable PLL clock, U14
Main power fuse @2.5A/16V, F1
cPCI connector, J1
cPCI connector, J4
cPCI connector, J5
cPCI connector, J6
FTDI FT601Q USB3 USB 3.0 to FIFO bridge, U9
TI THS5641 8bit DAC ,U28
TI THS5641 8bit DAC ,U31
TI THS5641 8bit DAC ,U29
TI THS5641 8bit DAC ,U33
Marvell Alaska 88E1512 GbE PHY ,U20
Initial Delivery State
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Table_1OV_IDS
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Table 1: Initial delivery state of programmable devices on the module
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Storage device name
Content
Notes
User configuration EEPROMs (1x Microchip 24AA128T-I/ST, 1x Microchip 24AA025E48T-I/OT)
Empty
Not programmed
USB2 to FIFO USB 2.0 to UART/JTAG bridge configuration EEPROM (ST M93C66)
Empty
Not programmed
Si5345A programmable PLL NVM OTP
Empty
Not programmed
2x QSPI Flash memory
Empty
Not programmed
...
To get started with TEC0850 board, some initial signals should be set decribed described in the following table:
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Table_2OV_CS
title
Table 2: TEC0850 Control Signals
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Control signal
Switch / Button
Signal Schematic Names
Connected to
Functionality
Notes
SC JTAGEN
S1-1
JTAGEN
SC FPGA U18, bank 1B, pin E5
OFF: MAX 10 JTAG enabled, ON: Zynq MPSoC JTAG enabled
-
EEPROM WP
S1-2
WP
EEPROM U63, pin 7
Write protect, active on OFF position
-
FPGA PUDC
S1-3
PUDC_B
Zynq MPSOC PS Config Bank 503, pin AD15
ON: internal pull-up resistors enabled, OFF: floating
-
SC Switch
S1-4
SW4
SC FPGA U18, bank 8, pin A5
low active logic
Reserved for future use
4bit boot mode setting code
S2-1
MODE3
Zynq MPSOC PS Config Bank 503, pin R23
Set 4-bit code for boot mode selection, most common modes are as follows:
Set DIP-switches as bit pattern "S1-4 | S1-3 | S1-2 | S1-1 : Boot Mode":
ON | ON | ON | ON : JTAG Boot ON | ON | ON | OFF : Quad-SPI ON | ON | OFF | OFF : SD Card
For carrier or stand-alone boards use subsection for every connector typ type (add designator on a description, not on the subsection title), for example:
SD
USB
ETH
FMC
...
For modules which needs need carrier us only classes and refer to B2B connector if more than one is used, for example
JTAG
UART
I2C
MGT
...
CompactPCI Serial Backplane Connectors
The TEC0850 board is equipped with 3 CompactPCI CompactPCI Serial high-speed backplane connectors which provides provide serial high-speed interconnects with transmission rates up to 12 Gb/s to the Zynq MPSoCs MGT lanes. On the cPCI connectors are also available single-ended Zynq MPSoC PL HP I/O's, high-speed USB2 USB 2.0 interface and single-ended FPGA I/Opins Zynq MPSoC and 's of the System Controller FPGA.
The connectors support single-ended and differential signaling as to the Zynq MPSoC PL HP banks 65 and 66 as those FPGA I/O's are routed from the FPGA banks as LVDS-pairs to the backplane connector.
The TEC0850 board is designed to be connected to the System Slot of the backplaneconnector, whereby 4 of the 6 connectors of the System Slot configuration are fitted to the TEC0850 board.
Following diagram gives an overview of the CompactPCI Serial backplane connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller FPGA U18:
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Figure_SIP_3CompactPCI
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Figure 3: TEC0850-02 CompactPCI I/O and high-speed interfacesinterfaces
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Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the cPCI connectors:
Supplied by 10-output PLL clock U14, optional if decoupling capacitors and resistors are fitted (see schematic), also shared with SC FPGA and header J13.
Anchor
CompactPCI Connector J3
CompactPCI Connector J3
CompactPCI Serial Connector J3
CompactPCI Serial connector J3 is not fitted on the TEC0850 board by default, but is necessary if the second optional USB2 PHY U13 if fitted and its USB2 differential serial data interface is connected to the cPCI connector J2.
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Table_5SIP_cPCI_J3_io
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Table 5: cPCI J1 clock signalscPCI J3 interfaces
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Interfaces
Clock Signal Schematic Name
cPCI Connector Pin
Header J13 Pin
SC FPGA U18 Pin
Notes
SATA_SL
SATA_SCL
J1-K3 J1-J3
J13-5 J13-1
Bank 1B, Pin G1 Bank 1B, Pin G2
Supplied by 10-output PLL clock U14,
cPCI connector J1 clock signal from PLL U14 is also shared with SC FPGA and header J13
Front panel USB-C Interface is connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.
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Figure_SIP_4usb3
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Figure 4: TEC0850-02 USB3 to FIFO bridge
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The USB3 The USB 3.0 to FIFO bridge FTDI FT601Q U9 is connected to the Zynq MPSoC's PL bank 64 and is accessible through USB-C connector J10:
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Table_10_SIP_j10_usb-c
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Table 10: USB-C connector J10
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Interface
Signal Schematic Names
Connected to
Notes
USB3 data lane
SSRX_P
SSRX_N
SSTXX_P
SSTXX_N
USB C Connector J10
-
USB2 data lane
SS_D_P
SS_D_N
USB C Connector J10
-
Control Lines
FTDI_RESET_N
WAKEUP_N
SIWU_N
TXE_N
RXF_N
WR_N
RD_N
OE_N
BE_0
BE_1
BE_2
BE_3
FIFO_CLK
PL bank 64
-
Parallel GPIO's
DATA0
.
.
DATA31
PL bank 64
32bit FIFO register
...
The Digilent plug-in software and cable drivers must be installed on your machine for you to be able to use JTAG interface.
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Figure 5: JTAG/UART Interface
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The USB2 to FIFO bridge FTDI FT2232H U4 is connected to the SC FPGA U18 and is accessible through Micro-USB2 connector J9:
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Table_SIP_11micro_usb2
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Table 11: Micro-USB2 connector J9
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Interface
Signal Schematic Names
Connected to
Notes
USB2 data lane
USB_P
USB_N
Micro-USB2 connector J9
-
Control Lines
FTDI_RST
SC FPGA U18, bank 6
-
Parallel GPIO's
ADBUS0
ADBUS1
ADBUS2
ADBUS3
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
SC FPGA U18, bank 6
-
...
The SD Card interface of the TEC0850 board is not directly wired to the connector J11 pins , but through a Texas Instruments TXS02612 SD IO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and MIO-bank of the Xilinx Zynq MPSoC. The Micro SD Card has 3.3V signal voltage level, but the PS MIO-bank on the Xilinx Zynq MPSoC has VCCIO of 1.8V.
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Figure_SIP_6microsd
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Figure 6: MicroSD Card interface
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There are some limitations to use SD card Interface in Linux.
...
Tip
To force Linux driver not to use this features add these features to add following instructions to device tree file.
&sdhci1 {
no-1-8-v; disable-wp; };
RJ45 - Ethernet
On-board Onboard Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 501. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the GbE PHY U20 status LED output.
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Figure_7SIP_eth
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Figure 7: Gigabit Ethernet Interface
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TEC0850 GbE
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DDR4 SODIMM Socket
On the TEC0850 board, there is a DDR4 memory interface U3 with a 64-bit databus data bus width available for SO-DIMM modules connected to the Zynq UltraScale+ DDRC hard memory controller.
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Figure_SIP_8ddr4
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Figure 8: DDR4 SDRAM SODIMM socket
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Following table gives an overview about of the memory interface I/O signals of the DDR4 SDRAM SO-DIMM Socket U3:
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Table_SIP_12ddr4
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Table 12: DDR4 SDRAM SO-DIMM socket U3
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DDR4 SDRAM I/O Signal
Signal Schematic Name
Connected to
Notes
Address inputs
DDR4-A0 ... DDR4-A16
PS DDR Bank 504
-
Bank address inputs
DDR4-BA0 / DDR4-BA1
-
Bank group inputs
DDR4-BG0 / DDR4-BG1
-
Differential clocks
DDR4-CLK0_P
DDR4-CLK0_N
DDR4-CLK1_P
DDR4-CLK1_N
2 x DDR4 clock
Data input/output
DQ0 ... DQ63
-
Check bit input/output
CB0 ... CB7
-
Data strobe (differential)
DDR4-DQS0_P
DDR4-DQS0_N
...
DDR4-DQS8_P
DDR4-DQS8_N
-
Data mask and data bus inversion
DDR4-DM0 ... DDR4-DM8
-
Serial address inputs
DDR4-SA0 ... DDR4-SA2
address range configuration on I²C bus
Control Signals
DDR4-CS_N0 / DDR4-CS_N1
chip selest select signal
DDR4-ODT0 / DDR4-ODT1
On-die termination enable
DDR4-RESET
nRESET
DDR4-PAR
Command and address parity input
DDR4-CKE0 / DDR4-CKE1
Clock enableEnable
DDR4-ALERT
CRC error flag
DDR4-ACT
Activation command input
DDR4-EVENT
Temperature event
I²C
DDR4-SCL
DDR4-SDA
not connected
-
...
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Figure 9: 4x 8bit DAC units
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26-Pin IDC Header
There is a 26-pin IDC header (2x13, 1.27mm grid size) J16 available on the TEC0850 board which exposes the 20 FPGA HD I/O's of PL bank 47 to the user. The PL bank 47 has 3.3V VCCO bank voltage, on the header J16 there also the voltage levels 3.3V and 5V available. The I/O's can be accessed with a corresponding IDC connector.
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Figure 10: Zynq MPSoC PL I/O's IDC pin-header
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10-Pin Header
On the TEC0850 there is a 10-pin SMT header (2x5, 2.54mm grid size) J13 present which provides access to the JTAG and UART interface of Altera MAX10 System Controller FPGA. The header J13 has a compatible pin assignment to the TEI0004 JTAG programmer for Altera FPGAs, the voltage levels 3.3V is on the header available as a reference I/O-voltage for JTAG and UART.
The 4 JTAG pins of the header J13 are also connected to the cPCI connector J1 and can be used es as user GPIO's of the SC FPGA U18 with othr other functionalities then JTAG.
On the header J13, there is also a optional reference clock signal from PLL clcok clock U14 available, which can be also if the necessary resistors and capacitors are fitted on board. The clock can also be used for the SC FPGA U18 and on the cPCI connector J1.
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Figure 11: 10-pin JTAG/UART header
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3-Pin PicoBlade Header
2 I/O's of the SC FPGA U18 are exposed to the on-board 3-Pin PicoBlade header J8 available to the user or for future use of upcoming versions of SC FPGA firmware.
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Figure 12: 3-pin PicoBlade header
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Battery Holder
There is a CR1220 battery holder available to the supply the voltage for the for for the Zynq MPSoC's Battery Power Domain (BBRAM and RTC). The battery voltage VBATT should be in the range of 2.2V to 5.5V, use the 3.0V CR1220 battery.
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Figure 13: Backup-Battery Holder
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4-Wire PWM FAN Connectors
The TEC0850 offers one 4-wire PWM FAN connector FPGA cooling fan controlled by SC FPGA U18:
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Figure 14: 4-wire PWM FAN connector
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Onboard Peripherals
Page properties
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Notes :
add a subsection for every component which is important for design, for example:
Ethernet PHY
USB PHY
Programmable Clock Generator
Oscillators
eMMCs
RTC
FTDI
...
DIP-Switches
Buttons
LEDs
...
The PS MIO pins are routed to the on-board onboard peripherals as follows:
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Table 13: Default MIO Configuration
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PS MIO
Function
Connected to
0
SPI0QSPI*
U24-B2, CLK
1
SPI0QSPI*
U24-D2, DO/IO1
2
SPI0QSPI*
U24-C4, WP/IO2
3
SPI0QSPI*
U24-D4, HOLD/IO3
4
SPI0QSPI*
U24-D3, DI/IO0
5
SPI0QSPI*
U24-C2, CS
6
-
Not not connected
7
SPI1QSPI*
U25-C2, CS
8
SPI1QSPI*
U25-D3, DI/IO0
9
SPI1QSPI*
U25-D2, DO/IO1
10
SPI1QSPI*
U17-C4, WP/IO2
11
SPI1QSPI*
U25-D4, HOLD/IO3
12
SPI1QSPI*
U25-B2, CLK
13 ... 15
-
not connected
16
USB2 PHY Reset
USB2 PHY U11, pin27
17
-
USB2 PHY Reset
USB2 PHY U13, pin27 (optional, PHY not fitted by default)not used
18 ... 19
-
not connected
20 ...21
PS MIO I²C
I²C peripherals
22 ... 25
user MIO
SC FPGA U18, bank 2
26 ... 38
RGMII
GbE PHY U20
39 ... 44
-
not connected
45 ... 51
SD IO
MicroSD Card socket J11
52 ... 63
USB2 ULPI
USB2 PHY U11
64 ... 75
-
USB2 ULPI
USB2 PHY U13 (optional, PHY not fitted by default)not used
76 ... 77
ETH MDC / MDIO
GbE PHY U20
* Flash is used as QSPI dual parallel
MAX10 System Controller FPGA
The TEC0850 board is equipped with one System Controller FPGA (Intel MAX10 10M08SAU169C8G) with the schematic designators U18. The SC FPGA is the central system management unit where essential control signals are logically linked by the implemented logic in FPGA firmware, which generates output signals to control the system, the on-board onboard peripherals, and the interfaces. Interfaces like JTAG and UART between the FTDI FT2232H chip and to the Zynq MPSoC are by-passed, forwarded and controlled by the System Controller FPGA.
Other tasks of the System Controller FPGA are the monitoring of the power-on sequence and to display the programming state of the FPGA module. The functionalities and configuration of the pins depend depending on the SC FPGA's firmware. The documentation of the firmware of SC FPGA U18 contains detailed information on this matter.
The Sytem System Controller FPGA is connected to the Zynq Ultrascale+ MPSoC through MIO and PL pins. The signals of these pins are forwarded by the SC FPGA to control some of the on board onboard peripherals.
Following block diagram visualizes the connection of the SC FPGA with the Zynq Ultrascale+ MPSoC via 4 PS MIO pins (MIO22 ... 25), PS Config control signals and 10 singled ended PL HD bank 48 I/O pins (MAX_IO1 ... MAX_IO10):
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Figure 15: TEC0850 MAX10 System Controller FPGA
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Programmable Clock Generator
There is a Si5345A U14, Silicon Labs I2C programmable 10-output PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and on-board onboard peripherals.
The clock outputs OUT1 and OUT9 are distributed via clock buffer U16 and clock driver U14 to several PL and MGT banks:
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Table_OBP_15clk_buffer
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Table 15: Clock driver and buffer outputs
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Si53340 U16 Pin
Signal Schematic Name
Connected to
Clock Signal Direction
Note
Q0
CLK1_P
CLK1_N
U1, pin G8 U1, pin G7
Output
GTH bank 229 reference clock input
Q1
CLK2_P
CLK2_N
U1, pin Y8 U1, pin Y7
Output
PL HP bank 66 reference clock input
Q2
CLK3_P
CLK3_N
U1, pin U27 U1, pin U28
Output
PS GTR Bank 505 reference clock input
Q3
CLK4_P
CLK4_N
U1, pin L27 U1, pin L28
Output
GTH bank 129 reference clock input
LTC6957 U14 U73 Pin
OUT1
CK_PLL_P
CK_PLL_N
U1, pin AG5 U1, pin AG4
Output
PL HP bank 65 reference clock input
OUT2
CK_P
CK_N
Signal 'SATA_SL' Signal 'SATA_SCL'
Output
optional reference clock input to cPCI connector J1,
header J13 and SC FPGA U18
if decoupling capacitors and resistors are fitted (see schematic), also shared with SC FPGA and header J13
The clock generator U14 is programmable via the on-board onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.
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Table_OBP_si5345_16i2c
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Table 16: SI5345 I2C address
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I2C address
Chip
Description
0x69
U14 Si5345
Clock generator and distributor
...
The TEC0850 board is equipped several on-board onboard oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board onboard peripherals with reference clock-signals:
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Table_OBP_17osc
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Table 17: TEC0850 on-board oscillators
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Clock Source
Signal Schematic Name
Frequency
Clock Input Destination
SiTime SiT8008BI oscillator, U22
PS_CLK
33.333333 MHz
Zynq MPSoC U1 PS Config Bank 503, pin U24
SiTime SiT8008AI oscillator, U12
USB0_CLK
52.000000 MHz
USB2 transceiver PHY U11, pin 26
SiTime SiT8008AI oscillator, U16
OSCI
12.000000 MHz
FTDI FT2232H U4, pin 3
Kyocera CX3225SB30000, Y1
-
30.000 MHz
FTDI FT601Q U9, pin 21/22
CM-2012-2pad, Y2
-
32.768000 kHz
Zynq MPSoC U1 PS Config Bank 503, pin V21/V22
Kyocera CX3225SB26000, Y3
XAXB_P
XAXB_N
54.000 MHz
10-output PLL clock generator U14, pin 8/9
SiTime SiT8008BI oscillator, U21
ETH_CLKIN
25.000000 MHz
Gigabit Ethernet PHY U20, pin 34
ASVTX-12-A oscillator, U75
IN0_P
40.000 MHz
10-output PLL clock generator U14, pin 63
...
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Figure 17: TEC0850 on-board FTDI chips
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FT2232H
The TEC0850 board is equipped with the FTDI FT2232H USB2 to JTAG/UART adapter controller connected to micro-USB2 connector J9 to provide JTAG and UART access to the Xilinx UltraScale+ Zynq
...
SoC or Intel MAX10 (switchable over DIP) . There is also a 256-byte configuration EEPROM U6 wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI
...
datasheetto get information about the capacity of the FT2232H chip.
Warning
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license, the on-board onboard JTAG will not be accessible any more anymore with any Xilinx tools. Software tools from the FTDI website do not warn or ask for confirmation before erasing user EEPROM content.
...
Channel B can be used as UART Interface routed to SC FPGA U18, 11 I/O's of Channel B are is routed to are usable for example as GPIOs and other standard interfaces.
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Table_OBP_18ft2232
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Table 18: FT2232H interface connections
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FT2232H U3 Pin
Signal Schematic Name
Connected to
Notes
Pin 12, ADBUS0
ADBUS0
SC FPGA U18 bank 6, pin G9
JTAG interface
Pin 13, ADBUS1
ADBUS1
SC FPGA U18 bank 6, pin F10
Pin 14, ADBUS2
ADBUS2
SC FPGA U18 bank 6, pin E10
Pin 15, ADBUS3
ADBUS3
SC FPGA U18 bank 6, pin D9
Pin 32, BDBUS0
BDBUS0
SC FPGA U18 bank 6, pin B11
UART and user configurable
GPIO's
Pin 33, BDBUS1
BDBUS1
SC FPGA U18 bank 6, pin A12
Pin 34, BDBUS2
BDBUS2
SC FPGA U18 bank 6, pin B12
Pin 35, BDBUS3
BDBUS3
SC FPGA U18 bank 6, pin C11
Pin 37, BDBUS4
BDBUS4
SC FPGA U18 bank 6, pin B13
Pin 38, BDBUS5
BDBUS5
SC FPGA U18 bank 6, pin C12
Pin 39, BDBUS6
BDBUS6
SC FPGA U18 bank 6, pin C13
Pin 40, BDBUS7
BDBUS7
SC FPGA U18 bank 6, pin D11
Pin 42, BCBUS0
BCBUS0
SC FPGA U18 bank 6, pin D12
Pin 46, BCBUS1
BCBUS1
SC FPGA U18 bank 6, pin E13
Pin 47, BCBUS2
BCBUS2
SC FPGA U18 bank 6, pin E12
Pin 48, BCBUS3
BCBUS3
SC FPGA U18 bank 6, pin F13
Pin 49, BCBUS4
BCBUS4
SC FPGA U18 bank 6, pin F12
Pin 11, nRESET
FTDI_RST
SC FPGA U18 bank 6, pin E9
control signals
...
The TEC0850 board is equipped with the FTDI FT601Q USB3 to 32bit-FIFO adapter controller connected to USB-C connector J10 to provide access to the Zynq MPSoC PL HP I/O's of bank 64. Also, 13 control signals of the FTDI FT601Q are connected to the HP bank 64.
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Table_19OBP_ft601q
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Table 19: FT601Q interface connections
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FT601Q U9 Pin
Signal Schematic Name
Connected to
Notes
Pin 40, DATA0
DATA0
PL HP bank 64, pin AK1
user GPIO's
Pin 41, DATA1
DATA1
PL HP bank 64, pin AJ10
Pin 42, DATA2
DATA2
PL HP bank 64, pin AJ9
Pin 43, DATA3
DATA3
PL HP bank 64, pin AK7
Pin 44, DATA4
DATA4
PL HP bank 64, pin AK5
Pin 45, DATA5
DATA5
PL HP bank 64, pin AM1
Pin 46, DATA6
DATA6
PL HP bank 64, pin AL2
Pin 47, DATA7
DATA7
PL HP bank 64, pin AK4
Pin 50, DATA8
DATA8
PL HP bank 64, pin AN1
Pin 51, DATA9
DATA9
PL HP bank 64, pin AL3
Pin 52, DATA10
DATA10
PL HP bank 64, pin AK8
Pin 53, DATA11
DATA11
PL HP bank 64, pin AN2
Pin 54, DATA12
DATA12
PL HP bank 64, pin AP2
Pin 55, DATA13
DATA13
PL HP bank 64, pin AL7
Pin 56, DATA14
DATA14
PL HP bank 64, pin AL5
Pin 57, DATA15
DATA15
PL HP bank 64, pin AM4
Pin 60, DATA16
DATA16
PL HP bank 64, pin AN4
Pin 61, DATA17
DATA17
PL HP bank 64, pin AM5
Pin 62, DATA18
DATA18
PL HP bank 64, pin AM6
Pin 63, DATA19
DATA19
PL HP bank 64, pin AN3
Pin 64, DATA20
DATA20
PL HP bank 64, pin AP3
Pin 65, DATA21
DATA21
PL HP bank 64, pin AP4
Pin 66, DATA22
DATA22
PL HP bank 64, pin AP5
Pin 67, DATA23
DATA23
PL HP bank 64, pin AN6
Pin 69, DATA24
DATA24
PL HP bank 64, pin AN7
Pin 70, DATA25
DATA25
PL HP bank 64, pin AP6
Pin 71, DATA26
DATA26
PL HP bank 64, pin AP7
Pin 72, DATA27
DATA27
PL HP bank 64, pin AP11
Pin 73, DATA28
DATA28
PL HP bank 64, pin AP10
Pin 74, DATA29
DATA29
PL HP bank 64, pin AP9
Pin 75, DATA30
DATA30
PL HP bank 64, pin AN9
Pin 76, DATA31
DATA31
PL HP bank 64, pin AP8
Pin 58, CLK
FIFO_CLK
PL HP bank 64, pin AL6
control signals
Pin 4, BE0
BE_0
PL HP bank 64, pin AM10
Pin 5, BE1
BE_1
PL HP bank 64, pin AK10
Pin 6, BE2
BE_2
PL HP bank 64, pin AM11
Pin 7, BE3
BE_3
PL HP bank 64, pin AL11
Pin 13, nOE
OE_N
PL HP bank 64, pin AL8
Pin 12, nRD
RD_N
PL HP bank 64, pin AK9
Pin 11, nWR
WR_N
PL HP bank 64, pin AM9
Pin 8, nTXE
TXE_N
PL HP bank 64, pin AK12
Pin 9, nRXN
RXF_N
PL HP bank 64, pin AJ12
Pin 10, nSIWU
SIWU_N
PL HP bank 64, pin AL10
Pin 15, nRESET
FTDI_RESET_N
PL HP bank 64, pin AM8
Pin 16, nWAKEUP
WAKEUP_N
PL HP bank 64, pin AN8
...
On-board QSPI flash memory U24 and U25 on the TEC0850 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each, 64 MByte total QSPI Flash memory. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC, enabling dual parallel booting from QSPI Flash memory. This non volatile nonvolatile memory is used to store an initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
The TEC0850 board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip, the I²C interfaces is are connected to Zynq MPSoC bank 502 MIO 20...21 pins:
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Figure 19: On-board configuration EEPROMs
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The EEPROMs U63 and U64 are programmable via the on-board onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.
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Table_21OBP_eeprom_i2c
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Table 21: EEPROMs I²C Addresses
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I2C address
Chip
Description
0x50
U63 24AA128T-I/ST
128K Serial EEPROM
0x53
U64 24AA025E48T-I/OT
2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity
USB2 PHY
USB2 PHY U15 U11 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator U12.is supplied from the on-board 52.000000 MHz oscillator U12. There is also the option to equip the TEC0850 board with a second USB2 PHY U13 connected to the optional cPCI backplane connector J3. Both, the optional USB2 PHY U13 and cPCI connector J3 are not fitted by default.
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Figure 20: TEC0850 cPCI USB2 interface
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USB2 ULPI interface description
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USB2 PHY U11 Pin
Connected to
Notes
ULPI
PS bank MIO52 ... MIO63
Zynq Ultrascale+ USB0 MIO pins are connected to the PHY
REFCLK
-
52MHz from onboard oscillator U12
REFSEL[0..2]
-
All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETB
Zynq MPSoC MIO16, pin AM16
Low active USB2 PHY Reset
DP, DM
cPCI connector J1
USB2 data lane
CPEN
-
External USB power switch active-high enable signal
VBUS
5V
Connected to onboard 5V voltage level via a series of resistors, see schematic
ID
3.3V
USB2 OTG A-Device (host)
optional USB2 PHY U13
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Table_22
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Table 22: USB2 ULPI interface description
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PHY Pin
Connected to
Notes
ULPI
PS bank MIO52 MIO64 ... MIO63MIO75
Zynq Ultrascale+
USB0
USB1 MIO pins are connected to the PHY
REFCLK
-
52MHz from
on board
onboard oscillator U12
REFSEL[0..2]
-
All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETB
Zynq MPSoC MIO16MIO17, pin AM16AP16
Low active USB2 PHY Reset
DP, DM
optional cPCI connector J1J3
USB2 data lane
CPEN
-
External USB power switch active-high enable signal
VBUS
5V
Connected to USB VBUS onboard 5V voltage level via a series of resistors, see schematic
ID
3.3V
B-deviceUSB2 OTG A-Device (host)
Gigabit Ethernet PHY
On-board Onboard Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512, which use MDIO address 1.. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21.
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Figure 21: TEC0850 GbE interface with RJ-45 MegJack
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8bit DACs
The TEC0850 Board has 4 8-bit parallel Texas Instruments THS5641AIPW digital to analog converter (DAC) with up to 100 MSPS update rate connected to TI THS4631D operational amplifiers. See Schematic circuitry and TI THS5641 data sheet for proper operation of the on-board DAC units.
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Table_OBP_23dac_io
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Table 23: DAC units interface description
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DAC unit
Signal Schematic Name
Connected to
Functionality
DAC1
U28
DAC1_D0
PL HD bank 50, pin D11
Digital input bits D[7:0]
D7 is the most significant data bit (MSB), D0 is the least significant data bit (LSB).
DAC1_D1
PL HD bank 50, pin D10
DAC1_D2
PL HD bank 50, pin G11
DAC1_D3
PL HD bank 50, pin J11
DAC1_D4
PL HD bank 50, pin G10
DAC1_D5
PL HD bank 50, pin H10
DAC1_D6
PL HD bank 50, pin J10
DAC1_D7
PL HD bank 50, pin E10
DAC1_CLK
PL HD bank 50, pin F12
External clock input, input data latched on rising edge of the clock.
DAC1_MODE
PL HD bank 50, pin F10
Input code format (binary, twos complement)
EN_DAC1
SC FPGA U18 bank 8, pinE6
generate 3.3V voltages LDO U35, U34
DAC2
U31
DAC2_D0
PL HD bank 50, pin G15
Digital input bits D[7:0]
D7 is the most significant data bit (MSB), D0 is the least significant data bit (LSB).
DAC2_D1
PL HD bank 50, pin H14
DAC2_D2
PL HD bank 50, pin J14
DAC2_D3
PL HD bank 50, pin G14
DAC2_D4
PL HD bank 50, pin G13
DAC2_D5
PL HD bank 50, pin H13
DAC2_D6
PL HD bank 50, pin H12
DAC2_D7
PL HD bank 50, pin J12
DAC2_CLK
PL HD bank 50, pin F12
External clock input, input data latched on rising edge of the clock.
DAC2_MODE
PL HD bank 50, pin F11
Input code format (binary, twos complement)
EN_DAC2
SC FPGA U18 bank 8, pin E8
generate 3.3V voltages LDO U32, U60
DAC3
U29
DAC3_D0
PL HD bank 44, pin AG14
Digital input bits D[7:0]
D7 is the most significant data bit (MSB), D0 is the least significant data bit (LSB).
DAC3_D1
PL HD bank 44, pin AE13
DAC3_D2
PL HD bank 44, pin AG13
DAC3_D3
PL HD bank 44, pin AJ15
DAC3_D4
PL HD bank 44, pin AJ14
DAC3_D5
PL HD bank 44, pin AH14
DAC3_D6
PL HD bank 44, pin AL13
DAC3_D7
PL HD bank 44, pin AM13
DAC3_CLK
PL HD bank 44, pin AK15
External clock input, input data latched on rising edge of the clock.
DAC3_MODE
PL HD bank 44, pin AK14
Input code format (binary, twos complement)
EN_DAC3
SC FPGA U18 bank 8, pin B6
generate 3.3V voltages LDO U66, U68
DAC4
U33
DAC4_D0
PL HD bank 44, pin AP14
Digital input bits D[7:0]
D7 is the most significant data bit (MSB), D0 is the least significant data bit (LSB).
DAC4_D1
PL HD bank 44, pin AN14
DAC4_D2
PL HD bank 44, pin AM14
DAC4_D3
PL HD bank 44, pin AN13
DAC4_D4
PL HD bank 44, pin AP12
DAC4_D5
PL HD bank 44, pin AN12
DAC4_D6
PL HD bank 44, pin AF13
DAC4_D7
PL HD bank 44, pin AH13
DAC4_CLK
PL HD bank 44, pin AK13
External clock input, input data latched on rising edge of the clock.
DAC4_MODE
PL HD bank 44, pin AK13
Input code format (binary, twos complement)
EN_DAC4
SC FPGA U18 bank 8, pin A6
generate 3.3V voltages LDO U70, U72
...
There are two 4-bit DIP-witches S3 and S4 present on the TEC0850 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
Table The table below describes the functionalities of the switches of DIP-switches S1 and S2 at their each positionsevery position:
The TEC0850 board is equipped with several LEDs to signal current states and activities.
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Table_26OBP_leds
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Table 26: On-board LEDs description
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LED
Color
Connected to
Description and Notes
Front panel LED D1
Red
Zynq MPSoC PL bank 11, pin AF15
PL User defined LED
Front panel LED D2
Green
Zynq MPSoC PL bank 11, pin AG15
PL User defined LED
Front panel LED D3
Green
Zynq MPSoC PL bank 11, pin AE15
PL User defined LED
Front panel LED D4
Green
SC FPGA U18 bank 3, pin M4
Power Good
...
The maximum power consumption of a module mainly depends on the design running on the FPGA.
Xilinx provide provides a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
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Table_27PWR_PC
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Table 27: Typical power consumption
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Power Input
Typical Current
VIN_12V
TBD*
Power supply with a minimum current capability of 5A (60W@12V, CompactPCI Serial spec.) for system startup is recommended.
The TEC0850 board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet an embedded system power management requirement by advanced power management features. This These features allow to offset offsetting the power and heat constraints against overall performance and operational efficiency.
...
There are following dependencies how the initial 24V voltage from the main power pins on cPCI slot J1 is distributed to the on-board onboard DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:
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Figure 22: Power Distribution
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Power-On Sequence
The TEC0850 board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board onboard DC-DC converters dedicated to the particular Power Domains and powering up the on-board onboard voltages.
On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller FPGA U18:
...
Hence, those three power instances will be powered up consecutively when the Power-Good signals of the previous instance is are asserted.
Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.
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Figure 23: Power-On Sequence Diagram
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TEC0850 Power-On Sequence Diagram
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Warning
To avoid any damage to the MPSoC module, check for stabilized on-board voltages in steady onboard voltages in a steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/Os should be tri-stated during the power-on sequence.
It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning that all on-board onboard voltages have become stable and the module is properly powered up.
...
The voltages PS_1V8 and VCCINT_0V85 are monitored by the voltage monitor circuit U69, which generates the POR_B reset signal at power-on. A manual reset is also possible by driving the low active MR-pin connected to MAX10 FPGA U18 (bank5, pin K10) to GND.
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Figure_PWR_24PM
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Figure 24: TEC0850 voltage Voltage monitor circuit
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TEC0850 Voltage Monitor Circuit
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Power Rails
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Table_28PWR_PR
title
Table 28: TEC0850 power rails description
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Connector / Pin
Voltage
Direction
Notes
J1, pin A1, D1, E1, G1, H1, J1, K1
VIN_12V
Input
Main power supply pins
J17, pin 2
12V
Output
4-wire PWM fan connector supply voltage
J13, pin 4
+3V_D
Output
JTAG/UART reference VCCIO voltage
B1, pin +
VBATT
Input
3.0V CR1220 battery
J16, pin 2
5V
Output
I/O header VCCIO
J16, pin 1
3.3V
Output
I/O header VCCIO
J9, pin 4
VBUS
Input
USB2 VBUS (5.0V nominal)
J10, pin A4, B9
VBUS30
Input
USB3 VBUS (5.0V nominal)
J11, pin 4
3.3V
Output
MicroSD Card VDD
J15, pin 2
DAC1_OUT
Output
DAC output
J15, pin 3
DAC2_OUT
Output
DAC output
J15, pin 4
DAC3_OUT
Output
DAC output
J15, pin 5
DAC4_OUT
Output
DAC output
Bank Voltages
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Table_29PWR_BV
title
Table 29: TEC0850 Zynq MPSoC and SC FPGA bank voltages
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Zynq MPSoC Bank
Type
Schematic Name
Voltage
Voltage Range
44
HD
3.3V
3.3V
fixed to 3.3V
47
HD
3.3V
3.3V
fixed to 3.3V
48
HD
3.3V
3.3V
fixed to 3.3V
49
HD
3.3V
3.3V
fixed to 3.3V
50
HD
3.3V
3.3V
fixed to 3.3V
64
HP
PL_1V8
1.8V
fixed to 1.8V
65
HP
PL_1V8
1.8V
fixed to 1.8V
66
HP
PL_1V8
1.8V
fixed to 1.8V
67
HP
PL_1V8
1.8V
fixed to 1.8V
500
MIO
PS_1V8
1.8V
fixed to 1.8V
501
MIO
PS_1V8
1.8V
fixed to 1.8V
502
MIO
PS_1V8
1.8V
fixed to 1.8V
503
CONFIG
PS_1V8
1.8V
fixed to 1.8V
504
PSDDR
DDR_1V2 DDR_PLL
1.2V 1.8V
fixed bank voltages
128
129
130
GTH
AVCC_L
AUX_L
AVTT_L
0.9V
1.8V
1.2V
fixed bank voltages
228
229
230
GTH
AVCC_R
AUX_R
AVTT_R
0.9V
1.8V
1.2V
fixed bank voltages
MAX10 FPGA Bank
Type
Schematic Name
Voltage
Voltage Range
1A
-
+3V_D
3.3V
fixed to 3.3V
1B
-
+3V_D
3.3V
fixed to 3.3V
2
-
PS_1V8
1.8V
fixed to 1.8V
3
-
3.3V
3.3V
fixed to 3.3V
5
-
+3V_D
3.3V
fixed to 3.3V
6
-
+3V_D
3.3V
fixed to 3.3V
8
-
+3V_D
3.3V
fixed to 3.3V
...
Absolute Maximum Ratings
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Table_TS_30AMR
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Table 30: Module absolute maximum ratings
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Parameter
Min
Max
Unit
Reference Document
Notes
VIN_12V
-0.3
16
V
Intel Enpirion EM2130 data sheet / Fuse F1
Fuse F1 @16V/2.5A
VBATT
-0.3
6
V
TPS780180300 data sheet
1.8V typical output
VCCO for HD I/O banks
-0.5
3.4
V
Xilinx document DS925
-
VCCO for HP I/O banks
-0.5
2
V
Xilinx document DS925
-
I/O input voltage for HD I/O banks
-0.55
VCCO + 0.55
V
Xilinx document DS925
-
I/O input voltage for HP I/O banks
-0.55
VCCO + 0.55
V
Xilinx document DS925
-
PS I/O input voltage (MIO pins)
-0.5
VCCO_PSIO + 0.55
V
Xilinx document DS925
VCCO_PSIO 1.8V nominally
PS GTR reference clocks absolute input voltage
-0.5
1.1
V
Xilinx document DS925
-
PS GTR absolute input voltage
-0.5
1.1
V
Xilinx document DS925
-
MGT clock absolute input voltage
-0.5
1.3
V
Xilinx document DS925
-
MGT Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage
-0.5
1.2
V
Xilinx document DS925
-
SC FPGA U18 I/O input voltage
-0.5
VCC + 0.5
V
Intel MAX 10 data sheet
VCC 3.3V nominally
Voltage A voltage on input I/O pins of DC-DC U17 EM2130 on header J12
-0.3
3.6
V
Intel Enpirion EM2130 data sheetEM2130 datasheet
-
Storage temperature (ambient)
-40
85
°C
ASVTX-12 data sheetdatasheet
-
Recommended Operating Conditions
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Table_TS_31ROC
title
Table 31: Module absolute maximum ratings
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Parameter
Min
Max
Unit
Reference Document
Notes
VIN_12V
12
14
V
Intel Enpirion EM2130 data sheetEM2130 datasheet
12V nominally input voltage
VBATT
2.2
5.5
V
TPS780180300 data sheet
supplied by 3.0V CR1220 battery
VCCO for HD I/O banks
1.14
3.4
V
Xilinx document DS925
-
VCCO for HP I/O banks
0.95
1.9
V
Xilinx document DS925
-
I/O input voltage for HD I/O banks
-0.2
VCCO + 0.2
V
Xilinx document DS925
-
I/O input voltage for HP I/O banks
-0.2
VCCO + 0.2
V
Xilinx document DS925
-
PS I/O input voltage (MIO pins)
-0.2
VCCO_PSIO + 0.2
V
Xilinx document DS925
VCCO_PSIO 1.8V nominally
SC FPGA U18 I/O input voltage
0
VCC
V
Intel MAX 10 data sheet
VCC 3.3V nominally
Board Operating Temperature Range 1), 2)
0
85
°C
Xilinx document DS925
extended grade Zynq MPSoC temperarure temperature range
1) Temperature range may vary depending on assembly options
2) The operating temperature range of the Zynq MPSoC, SC FPGA SoC and on-board onboard peripherals are a junction and also ambient operating temperature ranges
Physical Dimensions
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Figure_TS_25PD
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Figure 25: Physical dimensions drawing
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Comments
Set correct link to the shop page overview table of the product on English and German, if not available, set
Note this list must be only updated , if the document is online on public doc!
It's semi-automatically, so do the following
Add new row below first
Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is it will be deleted on newer pdf export template
Metadata is only used of for compatibility of older exports
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Table 34: Document change history
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Date
Revision
Constributor
Description
Page info
infoType
Modified date
dateFormat
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Page info
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Current version
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type
Flat
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Modified by
type
Flat
showVersions
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boot mode bugfix
2018-10-26
v.103
John Hartfiel
change" Compact PCI" to "Compact PCI Serial"
v.102
Ali Naseri
small corrections
v.101
John Hartfiel
style changes
v.97
Ali Naseri
added information about the optional second USB2 PHY and cPCI connector J2 (not fitted by default)
