TRM Name always "TE Series Name" +TRM, for example, "TE0720 TRM"
...
Page properties
hidden
true
id
Comments
Important General Note:
If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add a note, that this part is configurable
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
Figure template:
Scroll Title
anchor
Figure_x
title
Figure x: Text
Scroll Ignore
Create DrawIO object here: Attention if you copy from another page, use
Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until a scroll pdf export bug is fixed
Scroll Ignore
Create DrawIO object here: Attention if you copy from another page, use
Table template:
Layout macro can be used for a landscape of large tables
Set column width manually(can be used for small tables to fit over the whole page) or leave empty (automatically)
Scroll Title
anchor
Table_x
title
Table x: Text
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Example
Comment
1
2
...
The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
<type>_<main section>_<name>
type: Figure, Table
main section:
"OV" for Overview
"SIP" for Signal Interfaces and Pins,
"OBP" for On board Peripherals,
"PWR" for Power and Power-On Sequence,
"B2B" for Board to Board Connector,
"TS" for Technical Specification
"VCP" for Variants Currently in Production
"RH" for Revision History
name: custom, some fix names, see below
Fix names:
"Figure_OV_BD" for Block Diagram
"Figure_OV_MC" for Main Components
"Table_OV_IDS" for Initial Delivery State
"Table_PWR_PC" for Power Consumption
"Figure_PWR_PD" for Power Distribution
"Figure_PWR_PS" for Power Sequence
"Figure_PWR_PM" for Power Monitoring
"Table_PWR_PR" for Power Rails
"Table_PWR_BV" for Bank Voltages
"Table_TS_AMR" for Absolute_Maximum_Ratings
"Table_TS_ROC" for Recommended_Operating_Conditions
"Figure_TS_PD" for Physical_Dimensions
"Table_VCP_SO" for TE_Shop_Overview
"Table_RH_HRH" for Hardware_Revision_History
"Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
The Trenz Electronic TEC0850 board is a CompactPCI Serial card (3U form factor) integrating a Xilinx Zynq UltraScale+ MPSoC, one DDR4 SDRAM SODIMM socket with 64bit wide data bus, max. dual 512 MByte Flash memory for configuration and operation, 24 Gigabit transceivers on PL side and 4 on PS side, powerful switch-mode power supplies for all onboard voltages, USB2 and USB3 FIFO bridges and a large number of configurable I/Os available on the CompactPCI Serial backplane connectors.
Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.
...
Zynq UltraScale+ MPSoC ZU15
Front side interface connectors
RJ-45 GbE Ethernet interface
Circular push/pull connector with 4x on-board 8bit DAC output
MicroSD Card connector
USB 2.0 and USB 3.0 to FIFO bridge connector
4x status LEDs
4 CompactPCI Serial connectors for backplane connection (3U form factor)
24 GTH lanes
4 PS GTR lanes
USB 2.0 interface
64 Zynq PL HP I/O's
8x PLL clock input
JTAG, I²C and 7 user I/O's to MAX10 FPGA
64bit DDR4 SODIMM (PS connected), 8 GByte maximum
Dual parallel QSPI Flash (bootable), 512 MByte maximum
26-pin header with 20 Zynq PL HD I/O's
3-pin header with 2 MAX10 FPGA I/O's
System Controller (Altera MAX10 FPGA SoC)
Power Sequencing
System management and control for MPSoC and onboard peripherals
Si5345 programmable 10 output PLL clock generator
Si53340 Quad clock buffer
2x 4bit DIP switches
1x user push button
Zynq MPSoC cooling FAN connector
On-board high-efficiency DC-DC converters
Block Diagram
Scroll Title
anchor
Figure_OV_1BD
title
Figure 1: TEC0850-02 block diagram
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
56
diagramName
TEC0850 overview
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
scroll-only
Image Removed
Main Components
Page properties
hidden
true
id
Comments
Notes :
Picture of the PCB (top and bottom side) with labels of important components
Add List below
...
Scroll Title
anchor
Figure_2OV_MC
title
Figure 2: TEC0850-02 main components
Scroll Only
Image Added
Scroll Ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
5
diagramName
TEC0850 main components
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
GbE RJ-45 MagJack, J7
5-pin circular push/pull receptacle connector for DAC output, J15
Micro USB 2.0 B receptacle connector, J9
MicroSD Card socket, J11
USB 3.0 Type C connector, J10
LED light pipes J14 integrating LEDs D1 ... D4
4bit DIP-switch, S2
4bit DIP-switch, S1
FTDI FT2232 USB 2.0 to UART/JTAG bridge, U4
3-pin PicoBlade header, J8
MAX10 FPGA JTAG/UART 10-pin header, J13
Altera MAX10 System Controller FPGA, U18
4-Wire PWM fan connector, J17
26-pin IDC header for FPGA PL I/O's, J16
DDR4 SO-DIMM 260-pin socket, U3
Battery Holder CR1220, B1
256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U24
256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U25
DC-DC Converter LT8471IFE @+5VA/-5VA, U74
DC-DC Converter EM2130L02QI @VCCINT_0V85, U17
DC-DC Converter 171050601 @5V, U50
Xilinx Zynq Ultrascale+ MPSoC, U1
Si5345A 10-output I²C programmable PLL clock, U14
Main power fuse @2.5A/16V, F1
cPCI connector, J1
cPCI connector, J4
cPCI connector, J5
cPCI connector, J6
FTDI FT601Q USB 3.0 to FIFO bridge, U9
TI THS5641 8bit DAC ,U28
TI THS5641 8bit DAC ,U31
TI THS5641 8bit DAC ,U29
TI THS5641 8bit DAC ,U33
Marvell Alaska 88E1512 GbE PHY ,U20
Initial Delivery State
Scroll Title
anchor
Table_1OV_IDS
title
Table 1: Initial delivery state of programmable devices on the module
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Storage device name
Content
Notes
User configuration EEPROMs (1x Microchip 24AA128T-I/ST, 1x Microchip 24AA025E48T-I/OT)
Empty
Not programmed
USB 2.0 to UART/JTAG bridge configuration EEPROM (ST M93C66)
Empty
Not programmed
Si5345A programmable PLL NVM OTP
Empty
Not programmed
2x QSPI Flash memory
Empty
Not programmed
...
To get started with TEC0850 board, some initial signals should be set described in the following table:
Scroll Title
anchor
Table_OV_2CS
title
Table 2: TEC0850 Control Signals
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Control signal
Switch / Button
Signal Schematic Names
Connected to
Functionality
Notes
SC JTAGEN
S1-1
JTAGEN
SC FPGA U18, bank 1B, pin E5
OFF: MAX 10 JTAG enabled, ON: Zynq MPSoC JTAG enabled
-
EEPROM WP
S1-2
WP
EEPROM U63, pin 7
Write protect, active on OFF position
-
FPGA PUDC
S1-3
PUDC_B
Zynq MPSOC PS Config Bank 503, pin AD15
ON: internal pull-up resistors enabled, OFF: floating
-
SC Switch
S1-4
SW4
SC FPGA U18, bank 8, pin A5
low active logic
Reserved for future use
4bit boot mode setting code
S2-1
MODE3
Zynq MPSOC PS Config Bank 503, pin R23
Set 4-bit code for boot mode selection, most common modes are as follows:
Set DIP-switches as bit pattern "S1-4 | S1-3 | S1-2 | S1-1 : Mode":
ON | ON | ON | ON : JTAG Boot ON | ON | ON | OFF : Quad-SPI ON | ON | OFF | OFF : SD Card
For carrier or stand-alone boards use subsection for every connector type (add designator on a description, not on the subsection title), for example:
SD
USB
ETH
FMC
...
For modules which need carrier us only classes and refer to B2B connector if more than one is used, for example
JTAG
UART
I2C
MGT
...
CompactPCI Serial Backplane Connectors
The TEC0850 board is equipped with 3 CompactPCI CompactPCI Serial high-speed backplane connectors which provide serial high-speed interconnects with transmission rates up to 12 Gb/s to the Zynq MPSoCs MGT lanes. On the cPCI connectors are also available single-ended Zynq MPSoC PL HP I/O's, high-speed USB 2.0 interface , and single-ended FPGA I/Opins Zynq MPSoC and 's of the System Controller FPGA.
The connectors support single-ended and differential signaling as to the Zynq MPSoC PL HP banks 65 and 66 as those FPGA I/O's are routed from the FPGA banks as LVDS-pairs to the backplane connector.
The TEC0850 board is designed to be connected to the System Slot of the backplaneconnector, whereby 4 of the 6 connectors of the System Slot configuration are fitted to the TEC0850 board.
Following diagram gives an overview of the CompactPCI Serial backplane connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller FPGA U18:
Scroll Title
anchor
Figure_3SIP_CompactPCI
title
Figure 3: TEC0850-02 CompactPCI I/O and high-speed interfaces
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
1718
diagramName
IO Diagram
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
642
Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the cPCI connectors:
Supplied by 10-output PLL clock U14, optional if decoupling capacitors and resistors are fitted (see schematic), also shared with SC FPGA and header J13.
Anchor
CompactPCI Connector J3
CompactPCI Connector J3
CompactPCI Serial Connector J3
CompactPCI Serial connector J3 is not fitted on the TEC0850 board by default, but is necessary if the second optional USB2 PHY U13 if fitted and its USB2 differential serial data interface is connected to the cPCI connector J2.
Scroll Title
anchor
Table_5SIP_cPCI_J3_io
title
Table 5: cPCI J1 clock signalscPCI J3 interfaces
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Interfaces
Clock Signal Schematic Name
cPCI Connector Pin
Header J13 Pin
SC FPGA U18 Pin
Notes
I/O Signal Count
LVDS-pairs count
Connected to
VCCO bank Voltage
Notes
USB2
-
1 (RX/TX)
USB2 PHY U13
-
USB2 OTG A-Device (host)
SATA_SL
SATA_SCL
J1-K3 J1-J3
J13-5 J13-1
Bank 1B, Pin G1 Bank 1B, Pin G2
Supplied by 10-output PLL clock U14,
cPCI connector J1 clock signal from PLL U14 is also shared with SC FPGA and header J13
The USB 3.0 to FIFO bridge FTDI FT601Q U9 is connected to the Zynq MPSoC's PL bank 64 and is accessible through USB-C connector J10:
Scroll Title
anchor
Table_10SIP_j10_usb-c
title
Table 10: USB-C connector J10
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Interface
Signal Schematic Names
Connected to
Notes
USB3 data lane
SSRX_P
SSRX_N
SSTXX_P
SSTXX_N
USB C Connector J10
-
USB2 data lane
SS_D_P
SS_D_N
USB C Connector J10
-
Control Lines
FTDI_RESET_N
WAKEUP_N
SIWU_N
TXE_N
RXF_N
WR_N
RD_N
OE_N
BE_0
BE_1
BE_2
BE_3
FIFO_CLK
PL bank 64
-
Parallel GPIO's
DATA0
.
.
DATA31
PL bank 64
32bit FIFO register
...
The Digilent plug-in software and cable drivers must be installed on your machine for you to be able to use JTAG interface.
Scroll Title
anchor
Figure_SIP_jtag_5uart
title
Figure 5: JTAG/UART Interface
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
8
diagramName
uart_jtag
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
642
Scroll Only
Image Removed
The USB2 to FIFO bridge FTDI FT2232H U4 is connected to the SC FPGA U18 and is accessible through Micro-USB2 connector J9:
Scroll Title
anchor
Table_11SIP_micro_usb2
title
Table 11: Micro-USB2 connector J9
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Interface
Signal Schematic Names
Connected to
Notes
USB2 data lane
USB_P
USB_N
Micro-USB2 connector J9
-
Control Lines
FTDI_RST
SC FPGA U18, bank 6
-
Parallel GPIO's
ADBUS0
ADBUS1
ADBUS2
ADBUS3
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
SC FPGA U18, bank 6
-
...
The SD Card interface of the TEC0850 board is not directly wired to the connector J11 pins but through a Texas Instruments TXS02612 SD IO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and MIO-bank of the Xilinx Zynq MPSoC. The Micro SD Card has 3.3V signal voltage level, but the PS MIO-bank on the Xilinx Zynq MPSoC has VCCIO of 1.8V.
Scroll Title
anchor
Figure_SIP_6microsd
title
Figure 6: MicroSD Card interface
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
2
diagramName
TEC0850 SD IO
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
There are some limitations to use SD card Interface in Linux.
...
Onboard Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 501. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the GbE PHY U20 status LED output.
Scroll Title
anchor
Figure_SIP_7eth
title
Figure 7: Gigabit Ethernet Interface
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
2
diagramName
TEC0850 GbE
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
DDR4 SODIMM Socket
On the TEC0850 board, there is a DDR4 memory interface U3 with a 64-bit data bus width available for SO-DIMM modules connected to the Zynq UltraScale+ DDRC hard memory controller.
Scroll Title
anchor
Figure_SIP_8ddr4
title
Figure 8: DDR4 SDRAM SODIMM socket
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
1
diagramName
TEC0850 DDR4 interface
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
Following table gives an overview of the memory interface I/O signals of the DDR4 SDRAM SO-DIMM Socket U3:
Scroll Title
anchor
Table_12SIP_ddr4
title
Table 12: DDR4 SDRAM SO-DIMM socket U3
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
DDR4 SDRAM I/O Signal
Signal Schematic Name
Connected to
Notes
Address inputs
DDR4-A0 ... DDR4-A16
PS DDR Bank 504
-
Bank address inputs
DDR4-BA0 / DDR4-BA1
-
Bank group inputs
DDR4-BG0 / DDR4-BG1
-
Differential clocks
DDR4-CLK0_P
DDR4-CLK0_N
DDR4-CLK1_P
DDR4-CLK1_N
2 x DDR4 clock
Data input/output
DQ0 ... DQ63
-
Check bit input/output
CB0 ... CB7
-
Data strobe (differential)
DDR4-DQS0_P
DDR4-DQS0_N
...
DDR4-DQS8_P
DDR4-DQS8_N
-
Data mask and data bus inversion
DDR4-DM0 ... DDR4-DM8
-
Serial address inputs
DDR4-SA0 ... DDR4-SA2
address range configuration on I²C bus
Control Signals
DDR4-CS_N0 / DDR4-CS_N1
chip select signal
DDR4-ODT0 / DDR4-ODT1
On-die termination enable
DDR4-RESET
nRESET
DDR4-PAR
Command and address parity input
DDR4-CKE0 / DDR4-CKE1
Clock Enable
DDR4-ALERT
CRC error flag
DDR4-ACT
Activation command input
DDR4-EVENT
Temperature event
I²C
DDR4-SCL
DDR4-SDA
not connected
-
...
Scroll Title
anchor
Figure_9SIP_dac
title
Figure 9: 4x 8bit DAC units
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
3
diagramName
TEC0850 DACs
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
26-Pin IDC Header
There is a 26-pin IDC header (2x13, 1.27mm grid size) J16 available on the TEC0850 board which exposes the 20 FPGA HD I/O's of PL bank 47 to the user. The PL bank 47 has 3.3V VCCO bank voltage, on the header J16 there also the voltage levels 3.3V and 5V available. The I/O's can be accessed with a corresponding IDC connector.
Scroll Title
anchor
Figure_10_SIP_idc_mpsoc_pl
title
Figure 10: Zynq MPSoC PL I/O's IDC pin-header
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
3
diagramName
TEC0850 header J16
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
10-Pin Header
On the TEC0850 there is a 10-pin SMT header (2x5, 2.54mm grid size) J13 present which provides access to the JTAG and UART interface of Altera MAX10 System Controller FPGA. The header J13 has a compatible pin assignment to the TEI0004 JTAG programmer for Altera FPGAs, the voltage levels 3.3V is on the header available as a reference I/O-voltage for JTAG and UART.
...
On the header J13, there is also a optional reference clock signal from PLL clock U14 available, which can be also if the necessary resistors and capacitors are fitted on board. The clock can also be used for the SC FPGA U18 and on the cPCI connector J1.
Scroll Title
anchor
Figure_11SIP_10pin_jtag_uart
title
Figure 11: 10-pin JTAG/UART headerheader
Scroll Only
Image Added
Scroll Ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
34
diagramName
TEC0850 header 13
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
3-Pin PicoBlade Header
2 I/O's of the SC FPGA U18 are exposed to the on-board 3-Pin PicoBlade header J8 available to the user or for future use of upcoming versions of SC FPGA firmware.
Scroll Title
anchor
Figure_SIP_3pin_12picoblade
title
Figure 12: 3-pin PicoBlade header
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
1
diagramName
TEC0850 3-pin header J8
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
Battery Holder
There is a CR1220 battery holder available to the supply the voltage for the Zynq MPSoC's Battery Power Domain (BBRAM and RTC). The battery voltage VBATT should be in the range of 2.2V to 5.5V, use the 3.0V CR1220 battery.
Scroll Title
anchor
Figure_SIP_Battery_13Holder
title
Figure 13: Backup-Battery Holder
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
4
diagramName
TEC0850 battery holder
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
4-Wire PWM FAN Connectors
...
Scroll Title
anchor
Figure_14SIP_fan
title
Figure 14: 4-wire PWM FAN connector
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
2
diagramName
TEC0850 4-Wire PWM Connector
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
Onboard Peripherals
Page properties
hidden
true
id
Comments
Notes :
add a subsection for every component which is important for design, for example:
Ethernet PHY
USB PHY
Programmable Clock Generator
Oscillators
eMMCs
RTC
FTDI
...
DIP-Switches
Buttons
LEDs
...
The PS MIO pins are routed to the onboard peripherals as follows:
Scroll Title
anchor
Table_13OBP_default_mio
title
Table 13: Default MIO Configuration
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
PS MIO
Function
Connected to
0
SPI0QSPI*
U24-B2, CLK
1
SPI0QSPI*
U24-D2, DO/IO1
2
SPI0QSPI*
U24-C4, WP/IO2
3
SPI0QSPI*
U24-D4, HOLD/IO3
4
SPI0QSPI*
U24-D3, DI/IO0
5
SPI0QSPI*
U24-C2, CS
6
-
Not not connected
7
SPI1QSPI*
U25-C2, CS
8
SPI1QSPI*
U25-D3, DI/IO0
9
SPI1QSPI*
U25-D2, DO/IO1
10
SPI1QSPI*
U17-C4, WP/IO2
11
SPI1QSPI*
U25-D4, HOLD/IO3
12
SPI1QSPI*
U25-B2, CLK
13 ... 15
-
not connected
16
USB2 PHY Reset
USB2 PHY U11, pin27
17
-
USB2 PHY Reset
USB2 PHY U13, pin27 (optional, PHY not fitted by default)not used
18 ... 19
-
not connected
20 ...21
PS MIO I²C
I²C peripherals
22 ... 25
user MIO
SC FPGA U18, bank 2
26 ... 38
RGMII
GbE PHY U20
39 ... 44
-
not connected
45 ... 51
SD IO
MicroSD Card socket J11
52 ... 63
USB2 ULPI
USB2 PHY U11
64 ... 75
-
USB2 ULPI
USB2 PHY U13 (optional, PHY not fitted by default)not used
76 ... 77
ETH MDC / MDIO
GbE PHY U20
* Flash is used as QSPI dual parallel
MAX10 System Controller FPGA
...
Following block diagram visualizes the connection of the SC FPGA with the Zynq Ultrascale+ MPSoC via 4 PS MIO pins (MIO22 ... 25), PS Config control signals and 10 singled ended PL HD bank 48 I/O pins (MAX_IO1 ... MAX_IO10):
Scroll Title
anchor
Figure_OBP_max10_15sc
title
Figure 15: TEC0850 MAX10 System Controller FPGA
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
2
diagramName
TEC0850 SC TO Zynq connections
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
Programmable Clock Generator
There is a Si5345A U14, Silicon Labs I2C programmable 10-output PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and onboard peripherals.
Following table shows onboard Silicon Labs I2C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:
Scroll Title
anchor
Table_14OBP_si5345
title
Table 14: SI5345 Clock Outputs
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Si5345A U14 Pin
Signal Schematic Name
Connected to
Clock Signal Direction
Note
IN0
IN0_P
40.000 MHz Oscillator U75
Input
external reference clock input
IN0_N
GND
IN1
-
not connected
Input
not used
-
not connected
IN2
-
not connected
Input
not used
-
not connected
IN3
-
not connected
Input
not used
-
not connected
OUT0
CLK0_P
Quad clock buffer Si53340 U16
Output
reference clock input to Quad clock buffer
CLK0_N
OUT1
PE1_CLK_N
cPCI J5, pin B5
Output
reference clock output to cPCI connector J5
PE1_CLK_P
cPCI J5, pin A5
OUT2
PE5_CLK_N
cPCI J5, pin C6
Output
PE5_CLK_P
cPCI J5, pin B6
OUT3
PE2_CLK_N
cPCI J5, pin E5
Output
PE2_CLK_P
cPCI J5, pin D5
OUT4
PE3_CLK_N
cPCI J5, pin H5
Output
PE3_CLK_P
cPCI J5, pin G5
OUT5
PE4_CLK_N
cPCI J5, pin K5
Output
PE4_CLK_P
cPCI J5, pin J5
OUT6
PE6_CLK_N
cPCI J5, pin F6
Output
PE6_CLK_P
cPCI J5, pin E6
OUT7
PE8_CLK_N
cPCI J5, pin L6
Output
PE8_CLK_P
cPCI J5, pin K6
OUT8
PE7_CLK_N
cPCI J5, pin I6
Output
PE7_CLK_P
cPCI J5, pin H6
OUT9
CLK9_P
Clock Driver LTC6975 U73
Output
reference clock input to dual clock driver U73
CLK9_N
XA/XB
XAXB_P
54.000 MHz quartz oscillator Y3
Input
Differential quartz oscillator clock input
XAXB_N
SCLK, SDA/SDIO
I2C_SCL
I2C_SDA
MIO20
MIO21
BiDir
I²C address 0x69
The clock outputs OUT1 and OUT9 are distributed via clock buffer U16 and clock driver U14 to several PL and MGT banks:
Scroll Title
anchor
Table_OBP_clk_15buffer
title
Table 15: Clock driver and buffer outputs
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Si53340 U16 Pin
Signal Schematic Name
Connected to
Clock Signal Direction
Note
Q0
CLK1_P
CLK1_N
U1, pin G8 U1, pin G7
Output
GTH bank 229 reference clock input
Q1
CLK2_P
CLK2_N
U1, pin Y8 U1, pin Y7
Output
PL HP bank 66 reference clock input
Q2
CLK3_P
CLK3_N
U1, pin U27 U1, pin U28
Output
PS GTR Bank 505 reference clock input
Q3
CLK4_P
CLK4_N
U1, pin L27 U1, pin L28
Output
GTH bank 129 reference clock input
LTC6957 U14 U73 Pin
OUT1
CK_PLL_P
CK_PLL_N
U1, pin AG5 U1, pin AG4
Output
PL HP bank 65 reference clock input
OUT2
CK_P
CK_N
Signal 'SATA_SL' Signal 'SATA_SCL'
Output
optional reference clock input to cPCI connector J1,
header J13 and SC FPGA U18
if decoupling capacitors and resistors are fitted (see schematic), also shared with SC FPGA and header J13
The clock generator U14 is programmable via the onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.
Scroll Title
anchor
Table_OBP_16si5345_i2c
title
Table 16: SI5345 I2C address
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
I2C address
Chip
Description
0x69
U14 Si5345
Clock generator and distributor
...
The TEC0850 board is equipped several onboard oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the onboard peripherals with reference clock-signals:
Scroll Title
anchor
Table_OBP_17osc
title
Table 17: TEC0850 on-board oscillators
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Clock Source
Signal Schematic Name
Frequency
Clock Input Destination
SiTime SiT8008BI oscillator, U22
PS_CLK
33.333333 MHz
Zynq MPSoC U1 PS Config Bank 503, pin U24
SiTime SiT8008AI oscillator, U12
USB0_CLK
52.000000 MHz
USB2 transceiver PHY U11, pin 26
SiTime SiT8008AI oscillator, U16
OSCI
12.000000 MHz
FTDI FT2232H U4, pin 3
Kyocera CX3225SB30000, Y1
-
30.000 MHz
FTDI FT601Q U9, pin 21/22
CM-2012-2pad, Y2
-
32.768000 kHz
Zynq MPSoC U1 PS Config Bank 503, pin V21/V22
Kyocera CX3225SB26000, Y3
XAXB_P
XAXB_N
54.000 MHz
10-output PLL clock generator U14, pin 8/9
SiTime SiT8008BI oscillator, U21
ETH_CLKIN
25.000000 MHz
Gigabit Ethernet PHY U20, pin 34
ASVTX-12-A oscillator, U75
IN0_P
40.000 MHz
10-output PLL clock generator U14, pin 63
...
The TEC0850 board is equipped with 2 FTDI chips FT2232H (U4) and FT601Q (U9). Both chips are USB to Multipurpose UART/FIFO bridges which converts signals from USB2 or USB3 to a variety of standard serial and parallel interfaces.
Scroll Title
anchor
FigureFigure_OBP_17ft2232
title
Figure 17: TEC0850 on-board FTDI chips
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
4
diagramName
TEC0850 FT2232H
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
FT2232H
The TEC0850 board is equipped with the FTDI FT2232H USB2 to JTAG/UART adapter controller connected to micro-USB2 connector J9 to provide JTAG and UART access to the Xilinx UltraScale+ Zynq
...
SoC or Intel MAX10 (switchable over DIP) . There is also a 256-byte configuration EEPROM U6 wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI datasheet to get information about the capacity of the FT2232H chip.
Warning
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license, the onboard JTAG will not be accessible anymore with any Xilinx tools. Software tools from the FTDI website do not warn or ask for confirmation before erasing user EEPROM content.
...
Channel B can be used as UART Interface routed to SC FPGA U18, 11 I/O's of Channel B is routed to are usable for example as GPIOs and other standard interfaces.
Scroll Title
anchor
Table_OBP_18ft2232
title
Table 18: FT2232H interface connections
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
FT2232H U3 Pin
Signal Schematic Name
Connected to
Notes
Pin 12, ADBUS0
ADBUS0
SC FPGA U18 bank 6, pin G9
JTAG interface
Pin 13, ADBUS1
ADBUS1
SC FPGA U18 bank 6, pin F10
Pin 14, ADBUS2
ADBUS2
SC FPGA U18 bank 6, pin E10
Pin 15, ADBUS3
ADBUS3
SC FPGA U18 bank 6, pin D9
Pin 32, BDBUS0
BDBUS0
SC FPGA U18 bank 6, pin B11
UART and user configurable
GPIO's
Pin 33, BDBUS1
BDBUS1
SC FPGA U18 bank 6, pin A12
Pin 34, BDBUS2
BDBUS2
SC FPGA U18 bank 6, pin B12
Pin 35, BDBUS3
BDBUS3
SC FPGA U18 bank 6, pin C11
Pin 37, BDBUS4
BDBUS4
SC FPGA U18 bank 6, pin B13
Pin 38, BDBUS5
BDBUS5
SC FPGA U18 bank 6, pin C12
Pin 39, BDBUS6
BDBUS6
SC FPGA U18 bank 6, pin C13
Pin 40, BDBUS7
BDBUS7
SC FPGA U18 bank 6, pin D11
Pin 42, BCBUS0
BCBUS0
SC FPGA U18 bank 6, pin D12
Pin 46, BCBUS1
BCBUS1
SC FPGA U18 bank 6, pin E13
Pin 47, BCBUS2
BCBUS2
SC FPGA U18 bank 6, pin E12
Pin 48, BCBUS3
BCBUS3
SC FPGA U18 bank 6, pin F13
Pin 49, BCBUS4
BCBUS4
SC FPGA U18 bank 6, pin F12
Pin 11, nRESET
FTDI_RST
SC FPGA U18 bank 6, pin E9
control signals
...
The TEC0850 board is equipped with the FTDI FT601Q USB3 to 32bit-FIFO adapter controller connected to USB-C connector J10 to provide access to the Zynq MPSoC PL HP I/O's of bank 64. Also, 13 control signals of the FTDI FT601Q are connected to the HP bank 64.
The EEPROMs U63 and U64 are programmable via the onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.
Scroll Title
anchor
Table_21OBP_eeprom_i2c
title
Table 21: EEPROMs I²C Addresses
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
I2C address
Chip
Description
0x50
U63 24AA128T-I/ST
128K Serial EEPROM
0x53
U64 24AA025E48T-I/OT
2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity
USB2 PHY
USB2 PHY U15 U11 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator U12on-board 52.000000 MHz oscillator U12. There is also the option to equip the TEC0850 board with a second USB2 PHY U13 connected to the optional cPCI backplane connector J3. Both, the optional USB2 PHY U13 and cPCI connector J3 are not fitted by default.
Scroll Title
anchor
Figure_OBP_20usb2_phy
title
Figure 20: TEC0850 cPCI USB2 interface
Scroll Only
Image Added
Scroll Ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
12
diagramName
TEC0850 USB2 PHY
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Title
anchor
Table_OBP_usb2_phy_io
title
Scroll Only
Image Removed
Scroll Title
anchor
Table_22
title
Table 22: USB2 ULPI interface description
USB2 ULPI interface description
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
USB2 PHY U11 Pin
Connected to
Notes
ULPI
PS bank MIO52 ... MIO63
Zynq Ultrascale+ USB0 MIO pins are connected to the PHY
REFCLK
-
52MHz from onboard oscillator U12
REFSEL[0..2]
-
All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETB
Zynq MPSoC MIO16, pin AM16
Low active USB2 PHY Reset
DP, DM
cPCI connector J1
USB2 data lane
CPEN
-
External USB power switch active-high enable signal
VBUS
5V
Connected to onboard 5V voltage level via a series of resistors, see schematic
ID
3.3V
USB2 OTG A-Device (host)
optional USB2 PHY U13
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
PHY Pin
Connected to
Notes
ULPI
PS bank MIO52 MIO64 ... MIO63MIO75
Zynq Ultrascale+
USB0
USB1 MIO pins are connected to the PHY
REFCLK
-
52MHz from onboard oscillator U12
REFSEL[0..2]
-
All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETB
Zynq MPSoC MIO16MIO17, pin AM16AP16
Low active USB2 PHY Reset
DP, DM
optional cPCI connector J1J3
USB2 data lane
CPEN
-
External USB power switch active-high enable signal
VBUS
5V
Connected to USB VBUS onboard 5V voltage level via a series of resistors, see schematic
ID
3.3V
B-deviceUSB2 OTG A-Device (host)
Gigabit Ethernet PHY
Onboard Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512, which use MDIO address 1. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21.
Scroll Title
anchor
Figure_OBP_21eth_phy
title
Figure 21: TEC0850 GbE interface with RJ-45 MegJack
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
1
diagramName
TEC0850 GbE PHY
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
scroll-only
Image Removed
8bit DACs
The TEC0850 Board has 4 8-bit parallel Texas Instruments THS5641AIPW digital to analog converter (DAC) with up to 100 MSPS update rate connected to TI THS4631D operational amplifiers. See Schematic circuitry and TI THS5641 data sheet for proper operation of the on-board DAC units.
Scroll Title
anchor
Table_23OBP_dac_io
title
Table 23: DAC units interface description
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
DAC unit
Signal Schematic Name
Connected to
Functionality
DAC1
U28
DAC1_D0
PL HD bank 50, pin D11
Digital input bits D[7:0]
D7 is the most significant data bit (MSB), D0 is the least significant data bit (LSB).
DAC1_D1
PL HD bank 50, pin D10
DAC1_D2
PL HD bank 50, pin G11
DAC1_D3
PL HD bank 50, pin J11
DAC1_D4
PL HD bank 50, pin G10
DAC1_D5
PL HD bank 50, pin H10
DAC1_D6
PL HD bank 50, pin J10
DAC1_D7
PL HD bank 50, pin E10
DAC1_CLK
PL HD bank 50, pin F12
External clock input, input data latched on rising edge of the clock.
DAC1_MODE
PL HD bank 50, pin F10
Input code format (binary, twos complement)
EN_DAC1
SC FPGA U18 bank 8, pinE6
generate 3.3V voltages LDO U35, U34
DAC2
U31
DAC2_D0
PL HD bank 50, pin G15
Digital input bits D[7:0]
D7 is the most significant data bit (MSB), D0 is the least significant data bit (LSB).
DAC2_D1
PL HD bank 50, pin H14
DAC2_D2
PL HD bank 50, pin J14
DAC2_D3
PL HD bank 50, pin G14
DAC2_D4
PL HD bank 50, pin G13
DAC2_D5
PL HD bank 50, pin H13
DAC2_D6
PL HD bank 50, pin H12
DAC2_D7
PL HD bank 50, pin J12
DAC2_CLK
PL HD bank 50, pin F12
External clock input, input data latched on rising edge of the clock.
DAC2_MODE
PL HD bank 50, pin F11
Input code format (binary, twos complement)
EN_DAC2
SC FPGA U18 bank 8, pin E8
generate 3.3V voltages LDO U32, U60
DAC3
U29
DAC3_D0
PL HD bank 44, pin AG14
Digital input bits D[7:0]
D7 is the most significant data bit (MSB), D0 is the least significant data bit (LSB).
DAC3_D1
PL HD bank 44, pin AE13
DAC3_D2
PL HD bank 44, pin AG13
DAC3_D3
PL HD bank 44, pin AJ15
DAC3_D4
PL HD bank 44, pin AJ14
DAC3_D5
PL HD bank 44, pin AH14
DAC3_D6
PL HD bank 44, pin AL13
DAC3_D7
PL HD bank 44, pin AM13
DAC3_CLK
PL HD bank 44, pin AK15
External clock input, input data latched on rising edge of the clock.
DAC3_MODE
PL HD bank 44, pin AK14
Input code format (binary, twos complement)
EN_DAC3
SC FPGA U18 bank 8, pin B6
generate 3.3V voltages LDO U66, U68
DAC4
U33
DAC4_D0
PL HD bank 44, pin AP14
Digital input bits D[7:0]
D7 is the most significant data bit (MSB), D0 is the least significant data bit (LSB).
DAC4_D1
PL HD bank 44, pin AN14
DAC4_D2
PL HD bank 44, pin AM14
DAC4_D3
PL HD bank 44, pin AN13
DAC4_D4
PL HD bank 44, pin AP12
DAC4_D5
PL HD bank 44, pin AN12
DAC4_D6
PL HD bank 44, pin AF13
DAC4_D7
PL HD bank 44, pin AH13
DAC4_CLK
PL HD bank 44, pin AK13
External clock input, input data latched on rising edge of the clock.
DAC4_MODE
PL HD bank 44, pin AK13
Input code format (binary, twos complement)
EN_DAC4
SC FPGA U18 bank 8, pin A6
generate 3.3V voltages LDO U70, U72
...
The table below describes the functionalities of the switches of DIP-switches S1 and S2 at their every position:
The TEC0850 board is equipped with several LEDs to signal current states and activities.
Scroll Title
anchor
Table_26OBP_leds
title
Table 26: On-board LEDs description
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
LED
Color
Connected to
Description and Notes
Front panel LED D1
Red
Zynq MPSoC PL bank 11, pin AF15
PL User defined LED
Front panel LED D2
Green
Zynq MPSoC PL bank 11, pin AG15
PL User defined LED
Front panel LED D3
Green
Zynq MPSoC PL bank 11, pin AE15
PL User defined LED
Front panel LED D4
Green
SC FPGA U18 bank 3, pin M4
Power Good
...
Xilinx provides a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
Scroll Title
anchor
Table_PWR_27PC
title
Table 27: Typical power consumption
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Power Input
Typical Current
VIN_12V
TBD*
Power supply with a minimum current capability of 5A (60W@12V, CompactPCI Serial spec.) for system startup is recommended.
...
Scroll Title
anchor
Figure_22PWR_PD
title
Figure 22: Power Distribution
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
16
diagramName
Power supply
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
Scroll Only
Image Removed
Power-On Sequence
The TEC0850 board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the onboard DC-DC converters dedicated to the particular Power Domains and powering up the onboard voltages.
...
Scroll Title
anchor
Figure_23PWR_PS
title
Figure 23: Power-On Sequence Diagram
Scroll Only
Image Added
Scroll Ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
2
diagramName
TEC0850 Power-On Sequence Diagram
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
641
scroll-only
Image Removed
Warning
To avoid any damage to the MPSoC module, check for stabilized onboard voltages in a steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/Os should be tri-stated during the power-on sequence.
...
Scroll Title
anchor
Figure_24PWR_PM
title
Figure 24: TEC0850 voltage Voltage monitor circuit
scroll-only
Image Added
scroll-ignore
draw.io Diagram
border
false
viewerToolbar
true
fitWindow
false
diagramDisplayName
lbox
true
revision
1
diagramName
TEC0850 Voltage Monitor Circuit
simpleViewer
false
width
links
auto
tbstyle
hidden
diagramWidth
642
Scroll Only
Image Removed
Power Rails
Scroll Title
anchor
Table_PWR_28PR
title
Table 28: TEC0850 power rails description
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Connector / Pin
Voltage
Direction
Notes
J1, pin A1, D1, E1, G1, H1, J1, K1
VIN_12V
Input
Main power supply pins
J17, pin 2
12V
Output
4-wire PWM fan connector supply voltage
J13, pin 4
+3V_D
Output
JTAG/UART reference VCCIO voltage
B1, pin +
VBATT
Input
3.0V CR1220 battery
J16, pin 2
5V
Output
I/O header VCCIO
J16, pin 1
3.3V
Output
I/O header VCCIO
J9, pin 4
VBUS
Input
USB2 VBUS (5.0V nominal)
J10, pin A4, B9
VBUS30
Input
USB3 VBUS (5.0V nominal)
J11, pin 4
3.3V
Output
MicroSD Card VDD
J15, pin 2
DAC1_OUT
Output
DAC output
J15, pin 3
DAC2_OUT
Output
DAC output
J15, pin 4
DAC3_OUT
Output
DAC output
J15, pin 5
DAC4_OUT
Output
DAC output
Bank Voltages
Scroll Title
anchor
Table_29PWR_BV
title
Table 29: TEC0850 Zynq MPSoC and SC FPGA bank voltages
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Zynq MPSoC Bank
Type
Schematic Name
Voltage
Voltage Range
44
HD
3.3V
3.3V
fixed to 3.3V
47
HD
3.3V
3.3V
fixed to 3.3V
48
HD
3.3V
3.3V
fixed to 3.3V
49
HD
3.3V
3.3V
fixed to 3.3V
50
HD
3.3V
3.3V
fixed to 3.3V
64
HP
PL_1V8
1.8V
fixed to 1.8V
65
HP
PL_1V8
1.8V
fixed to 1.8V
66
HP
PL_1V8
1.8V
fixed to 1.8V
67
HP
PL_1V8
1.8V
fixed to 1.8V
500
MIO
PS_1V8
1.8V
fixed to 1.8V
501
MIO
PS_1V8
1.8V
fixed to 1.8V
502
MIO
PS_1V8
1.8V
fixed to 1.8V
503
CONFIG
PS_1V8
1.8V
fixed to 1.8V
504
PSDDR
DDR_1V2 DDR_PLL
1.2V 1.8V
fixed bank voltages
128
129
130
GTH
AVCC_L
AUX_L
AVTT_L
0.9V
1.8V
1.2V
fixed bank voltages
228
229
230
GTH
AVCC_R
AUX_R
AVTT_R
0.9V
1.8V
1.2V
fixed bank voltages
MAX10 FPGA Bank
Type
Schematic Name
Voltage
Voltage Range
1A
-
+3V_D
3.3V
fixed to 3.3V
1B
-
+3V_D
3.3V
fixed to 3.3V
2
-
PS_1V8
1.8V
fixed to 1.8V
3
-
3.3V
3.3V
fixed to 3.3V
5
-
+3V_D
3.3V
fixed to 3.3V
6
-
+3V_D
3.3V
fixed to 3.3V
8
-
+3V_D
3.3V
fixed to 3.3V
...
Absolute Maximum Ratings
Scroll Title
anchor
Table_TS_30AMR
title
Table 30: Module absolute maximum ratings
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Parameter
Min
Max
Unit
Reference Document
Notes
VIN_12V
-0.3
16
V
Intel Enpirion EM2130 data sheet / Fuse F1
Fuse F1 @16V/2.5A
VBATT
-0.3
6
V
TPS780180300 data sheet
1.8V typical output
VCCO for HD I/O banks
-0.5
3.4
V
Xilinx document DS925
-
VCCO for HP I/O banks
-0.5
2
V
Xilinx document DS925
-
I/O input voltage for HD I/O banks
-0.55
VCCO + 0.55
V
Xilinx document DS925
-
I/O input voltage for HP I/O banks
-0.55
VCCO + 0.55
V
Xilinx document DS925
-
PS I/O input voltage (MIO pins)
-0.5
VCCO_PSIO + 0.55
V
Xilinx document DS925
VCCO_PSIO 1.8V nominally
PS GTR reference clocks absolute input voltage
-0.5
1.1
V
Xilinx document DS925
-
PS GTR absolute input voltage
-0.5
1.1
V
Xilinx document DS925
-
MGT clock absolute input voltage
-0.5
1.3
V
Xilinx document DS925
-
MGT Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage
-0.5
1.2
V
Xilinx document DS925
-
SC FPGA U18 I/O input voltage
-0.5
VCC + 0.5
V
Intel MAX 10 data sheet
VCC 3.3V nominally
A voltage on input I/O pins of DC-DC U17 EM2130 on header J12
-0.3
3.6
V
Intel Enpirion EM2130 datasheet
-
Storage temperature (ambient)
-40
85
°C
ASVTX-12 datasheet
-
Recommended Operating Conditions
Scroll Title
anchor
Table_TS_31ROC
title
Table 31: Module absolute maximum ratings
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Parameter
Min
Max
Unit
Reference Document
Notes
VIN_12V
12
14
V
Intel Enpirion EM2130 datasheet
12V nominally input voltage
VBATT
2.2
5.5
V
TPS780180300 data sheet
supplied by 3.0V CR1220 battery
VCCO for HD I/O banks
1.14
3.4
V
Xilinx document DS925
-
VCCO for HP I/O banks
0.95
1.9
V
Xilinx document DS925
-
I/O input voltage for HD I/O banks
-0.2
VCCO + 0.2
V
Xilinx document DS925
-
I/O input voltage for HP I/O banks
-0.2
VCCO + 0.2
V
Xilinx document DS925
-
PS I/O input voltage (MIO pins)
-0.2
VCCO_PSIO + 0.2
V
Xilinx document DS925
VCCO_PSIO 1.8V nominally
SC FPGA U18 I/O input voltage
0
VCC
V
Intel MAX 10 data sheet
VCC 3.3V nominally
Board Operating Temperature Range 1), 2)
0
85
°C
Xilinx document DS925
extended grade Zynq MPSoC temperature range
...
Scroll Title
anchor
Figure_25TS_PD
title
Figure 25: Physical dimensions drawing
...
Page properties
hidden
true
id
Comments
Set correct link to the shop page overview table of the product on English and German, if not available, set
Note this list must be only updated if the document is online on public doc!
It's semi-automatically, so do the following
Add new row below first
Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point it will be deleted on newer pdf export template
Metadata is only used for compatibility of older exports
Scroll Title
anchor
Table_RH_34DCH
title
Table 34: Document change history
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
sortEnabled
false
cellHighlighting
true
Date
Revision
Constributor
Description
Page info
infoType
Modified date
dateFormat
yyyy-MM-dd
type
Flat
Page info
infoType
Current version
prefix
v.
type
Flat
showVersions
false
Page info
infoType
Modified by
type
Flat
showVersions
false
boot mode bugfix
2018-10-26
v.103
John Hartfiel
change" Compact PCI" to "Compact PCI Serial"
v.102
Ali Naseri
small corrections
v.101
John Hartfiel
style changes
v.97
Ali Naseri
added information about the optional second USB2 PHY and cPCI connector J2 (not fitted by default)
