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title	Table 21: EEPROMs I2C I²C Addresses

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I2C address	Chip	Description
0x50	U63 24AA128T-I/ST	128K Serial EEPROM
0x53	U64 24AA025E48T-I/OT	2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity

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Table below describes the functionalities of the switches of DIP-switches S1 and S2 at their each positions:

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title	Table x24: S2 TEC0850 DIP Switch-switches description

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DIP-switch S1	Signal Schematic Name	Connected to	Functionality	Notes
S1-1	JTAGEN	SC FPGA U18, bank 1B, pin E5	Positions: OFF: SC FPGA's JTAG enabled ON: SC FPGA's JTAG disabled	switch the JTAG pins to user GPIO's if JTAG is disabled
S1-2	WP	EEPROM U63, pin 7	Positions: OFF: Write Protect is enabled ON: Write Protect is disabled	-
S1-3	PUDC_B	Zynq MPSOC PS Config Bank 503, pin AD15	Positions: ON: PUDC_B is Low OFF: PUDC_B is HIGH	Internal pull-up resistors during configuration are enabled at ON-position,means I/O's are 3-stated until configuration of the FPGA completes.
S1-4	SW4	SC FPGA U18, bank 8, pin A5	SC Switch (Reserved for future use)	low active logic
DIP-switch S2	Signal Schematic Name	Connected to	Functionality	Notes
S2-1	MODE3	Zynq MPSOC PS Config Bank 503, pin R23	set 4-bit code for boot mode selection	See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description Set DIP-switches as bit pattern "S1-4 \| S1-3 \| S1-2 \| S1-1 : Boot Mode": ON \| ON \| ON \| ON : JTAG Boot Mode ON \| ON \| ON \| OFF : Quad-SPI ON \| ON \| OFF \| OFF : SD Card
S2-2	MODE2	Zynq MPSOC PS Config Bank 503, pin T23
S2-3	MODE1	Zynq MPSOC PS Config Bank 503, pin R22
S2-4	MODE0	Zynq MPSOC PS Config Bank 503, pin T22

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There is one switch button available to the user connected to the SC FPGA U18:

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title	Table x: LEDs25: On-board Push-Button

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Button

Connected to

Notes

S3

SC FPGA U18, bank 5, pin J10

low active logic

Refer documentation of the firmware of SC FPGA U18.

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The TEC0850 board is equipped with several LEDs to signal current states and activities.

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title	Table x26: On-board LEDs description

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LED	Color	Connected to	Description and Notes
Front panel LED D1	Red	Zynq MPSoC PL bank 11, pin AF15	PL User defined LED
Front panel LED D2	Green	Zynq MPSoC PL bank 11, pin AG15	PL User defined LED
Front panel LED D3	Green	Zynq MPSoC PL bank 11, pin AE15	PL User defined LED
Front panel LED D4	Green	SC FPGA U18 bank 3, pin M4	Power Good

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Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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title	Table x27: Typical power consumption.

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Power Input	Typical Current
VIN_12V	TBD*

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Power Rails

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title	Table x: Module absolute maximum ratings.28: TEC0850 power rails description

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Connector / Pin	Voltage	Direction	Notes
J1, pin A1, D1, E1, G1, H1, J1, K1	VIN_12V	Input	Main power supply pins
J17, pin 2	12V	Output	4-wire PWM fan connector supply voltage
J13, pin 4	+3V_D	Output	JTAG/UART reference VCCIO voltage
B1, pin +	VBATT	Input	3.0V CR1220 battery
J16, pin 2	5V	Output	I/O header VCCIO
J16, pin 1	3.3V	Output	I/O header VCCIO
J9, pin 4	VBUS	Input	USB2 VBUS (5.0V nominal)
J10, pin A4, B9	VBUS30	Input	USB3 VBUS (5.0V nominal)
J11, pin 4	3.3V	Output	MicroSD Card VDD
J15, pin 2	DAC1_OUT	Output	DAC output
J15, pin 3	DAC2_OUT	Output	DAC output
J15, pin 4	DAC3_OUT	Output	DAC output
J15, pin 5	DAC4_OUT	Output	DAC output

Bank Voltages

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title	Table x: Module absolute maximum ratings.29: TEC0850 Zynq MPSoC and SC FPGA bank voltages

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Zynq MPSoC Bank	Type	Schematic Name	Voltage	Voltage Range
44	HD	3.3V	3.3V	fixed to 3.3V
47	HD	3.3V	3.3V	fixed to 3.3V
48	HD	3.3V	3.3V	fixed to 3.3V
49	HD	3.3V	3.3V	fixed to 3.3V
50	HD	3.3V	3.3V	fixed to 3.3V
64	HP	PL_1V8	1.8V	fixed to 1.8V
65	HP	PL_1V8	1.8V	fixed to 1.8V
66	HP	PL_1V8	1.8V	fixed to 1.8V
67	HP	PL_1V8	1.8V	fixed to 1.8V
500	MIO	PS_1V8	1.8V	fixed to 1.8V
501	MIO	PS_1V8	1.8V	fixed to 1.8V
502	MIO	PS_1V8	1.8V	fixed to 1.8V
503	CONFIG	PS_1V8	1.8V	fixed to 1.8V
504	PSDDR	DDR_1V2 DDR_PLL	1.2V 1.8V	fixed bank voltages
128 129 130	GTH	AVCC_L AUX_L AVTT_L	0.9V 1.8V 1.2V	fixed bank voltages
228 229 230	GTH	AVCC_R AUX_R AVTT_R	0.9V 1.8V 1.2V	fixed bank voltages
MAX10 FPGA Bank	Type	Schematic Name	Voltage	Voltage Range
1A	-	+3V_D	3.3V	fixed to 3.3V
1B	-	+3V_D	3.3V	fixed to 3.3V
2	-	PS_1V8	1.8V	fixed to 1.8V
3	-	3.3V	3.3V	fixed to 3.3V
5	-	+3V_D	3.3V	fixed to 3.3V
6	-	+3V_D	3.3V	fixed to 3.3V
8	-	+3V_D	3.3V	fixed to 3.3V

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Absolute Maximum Ratings

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title	Table x30: Module absolute maximum ratings.

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Parameter	Min	Max	Unit	Reference Document	Notes
VIN_12V	-0.3	16	V	Intel Enpirion EM2130 data sheet / Fuse F1	Fuse F1 @16V/2.5A
VBATT	-0.3	6	V	TPS780180300 data sheet	1.8V typical output
VCCO for HD I/O banks	-0.5	3.4	V	Xilinx document DS925	-
VCCO for HP I/O banks	-0.5	2	V	Xilinx document DS925	-
I/O input voltage for HD I/O banks	-0.55	VCCO + 0.55	V	Xilinx document DS925	-
I/O input voltage for HP I/O banks	-0.55	VCCO + 0.55	V	Xilinx document DS925	-
PS I/O input voltage (MIO pins)	-0.5	VCCO_PSIO + 0.55	V	Xilinx document DS925	VCCO_PSIO 1.8V nominally
PS GTR reference clocks absolute input voltage	-0.5	1.1	V	Xilinx document DS925	-
PS GTR absolute input voltage	-0.5	1.1	V	Xilinx document DS925	-
MGT clock absolute input voltage	-0.5	1.3	V	Xilinx document DS925	-
MGT Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage	-0.5	1.2	V	Xilinx document DS925	-
SC FPGA U18 I/O input voltage	-0.5	VCC + 0.5	V	Intel MAX 10 data sheet	VCC 3.3V nominally
Voltage on input I/O pins of DC-DC U17 EM2130 on header J12	-0.3	3.6	V	Intel Enpirion EM2130 data sheet	-
Storage temperature (ambient)	-40	85	°C	ASVTX-12 data sheet	-

Recommended Operating Conditions

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title	Table x31: Module absolute maximum ratings.

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Parameter	Min	Max	Unit	Reference Document	Notes
VIN_12V	12	14	V	Intel Enpirion EM2130 data sheet	12V nominally input voltage, min. current 6.65A
VBATT	2.2	5.5	V	TPS780180300 data sheet	supplied by 3.0V CR1220 battery
VCCO for HD I/O banks	1.14	3.4	V	Xilinx document DS925	-
VCCO for HP I/O banks	0.95	1.9	V	Xilinx document DS925	-
I/O input voltage for HD I/O banks	-0.2	VCCO + 0.2	V	Xilinx document DS925	-
I/O input voltage for HP I/O banks	-0.2	VCCO + 0.2	V	Xilinx document DS925	-
PS I/O input voltage (MIO pins)	-0.2	VCCO_PSIO + 0.2	V	Xilinx document DS925	VCCO_PSIO 1.8V nominally
SC FPGA U18 I/O input voltage	0	VCC	V	Intel MAX 10 data sheet	VCC 3.3V nominally
Board Operating Temperature Range ^{1), 2)}	0	85	°C	Xilinx document DS925	extended grade Zynq MPSoC temperarure range

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Set correct link to the shop page overview table of the product on English and German, if not available, set
- https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/
- https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/

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title	Table x32: Shop Overview

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Trenz shop TE0xxx overview page
English page	German page

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Hardware Revision History

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title	Table x33: Module absolute maximum ratings.hardware revision history

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Date	Revision	Notes	PCN	Documentation Link
-	02	current available board revision	-	TEC0850-02
-	01	Prototypes	-	-

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

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title	Table x34: Document change history.

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Date

Revision

Constributor

Description

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infoType	Current version
prefix	v.
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change list

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all

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showVersions	false

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Trenz Electronic Documentation

Versions Compared

Old Version 76

New Version 77

Key

Power Rails

Bank Voltages

Absolute Maximum Ratings

Recommended Operating Conditions

Hardware Revision History