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The Trenz Electronic TE0808 is an industrial grade SoM integrating an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, MGT Transceivers and powerful DCDC power converters for most on-board voltages. A large number of configurable IOs is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.
Refer to https://trenz.org/te0808-info for the current online version of this manual and other available documentation.
1) Available as assembly variant or upon request.
2) Check whether the power supply is powerful enough for your FPGA design.
3) Without PCIe Core on PL, see AMD Product Selection Guide (XMP104)
4) Up to 8 GByte are possible with a maximum bandwidth of 2400 Mbit/s.
5) Dependent on the assembly option, a higher input voltage may be possible
Storage device | Designator | Content | Notes |
|---|---|---|---|
| Programmable Clock Generator | U5 | Not programmed | |
QSPI Flash | U7 / U17 | Not programmed | |
| EEPROM | U4 | MAC is burned-in by the manufacturer. |
Connector Type | Designator | Interface | IO count | Notes |
|---|---|---|---|---|
B2B | J1 | IO HP | 52x SE / 24x DIFF | Bank 66 |
B2B | J1 | MGT | 12x GTH (RX/TX) | |
B2B | J3 | IO MIO | 13x SE | Bank 500 |
B2B | J3 | IO MIO | 26x SE | Bank 501 |
B2B | J3 | IO MIO | 26x SE | Bank 502 |
B2B | J3 | IO HD | 48x SE / 24x DIFF | Bank 47 |
B2B | J3 | IO HD | 48x SE / 24x DIFF | Bank 48 |
B2B | J3 | MGT CLK | 3x DIFF | |
B2B | J3 | IO CLK in | 1x DIFF | |
B2B | J2 | MGT CLK | 3x DIFF | |
B2B | J2 | MGT | 4x GTH (RX/TX) | Bank 128 |
B2B | J2 | MGT | 4x GTR (RX/TX) | Bank 505 |
B2B | J2 | IO CLK out | 3x DIFF | |
B2B | J2 | IO CLK in | 1x DIFF | |
B2B | J4 | IO HP | 52x SE / 24x DIFF | Bank 64 |
B2B | J4 | IO HP | 52x SE / 24x DIFF | Bank 65 |
Test point | REV06 | REV05 signal | REV04 signal | REV03 signal | REV02 signal | Notes | ||
|---|---|---|---|---|---|---|---|---|
Top | Bottom | signal | ||||||
TP1 | x | PLL_SCL | ||||||
TP2 | x | PLL_SDA | ||||||
TP3 | x | LP_DCDC | ||||||
TP4 | x | DCDCIN | ||||||
TP5 | x | GND | ||||||
TP6 | x | TCK | ||||||
TP7 | x | PL_DCIN | ||||||
TP8 | x | GND | ||||||
TP9 | x | GT_DCDC | ||||||
TP10 | x | GND | ||||||
TP11 | x | TDI | ||||||
TP12 | x | TDO | ||||||
TP13 | x | TMS | ||||||
TP14 | x | PS_1V8 | ||||||
TP15 | x | U33.2 / U1A.V16 | Not used | GND | ||||
TP16 | x | FP_0V85 | Not used | |||||
TP17 | x | DDR_2V5 | Not used | |||||
TP18 | x | DDR_PLL | Not used | |||||
TP19 | x | PL_VCCINT | Not used | |||||
TP20 | x | AUX_R | Not used | |||||
TP21 | x | AVTT_R | Not used | |||||
TP22 | x | AUX_L | Not used | |||||
TP23 | x | DDR4-TEN | Not used | |||||
TP24 | x | AVCC_R | Not used | |||||
TP25 | x | PL_VCCINT | Not used | |||||
TP26 | x | AVTT_L | Not used | |||||
TP27 | - | - | Not used | |||||
TP28 | x | AVCC_L | Not used | |||||
TP29 | - | - | Not used | |||||
TP30 | x | PS_PLL | Not used | |||||
TP31 | x | PS_AVTT | Not used | |||||
TP32 | x | LP_0V85 | Not used | |||||
TP33 | x | PS_AUX | Not used | |||||
TP34 | x | PS_AVCC | Not used | |||||
TP35 | - | - | Not used | |||||
TP36 | x | POR_B | Not used | |||||
TP37 | x | PL_VCCINT | Not used | |||||
TP38 | x | PL_DCIN | Not used | |||||
TP39 | x | PL_1V8 | Not used | |||||
TP40 | x | DCDCIN | Not used | |||||
TP41 | x | DCDC_2V0 | Not used | |||||
TP42 | x | FP_0V85 | Not used | |||||
TP43 | x | PS_GT_1V0 | Not used | |||||
TP44 | x | GT_DCDC | Not used | |||||
TP45 | x | DDR_2V5 | Not used | |||||
TP46 | x | DDR_1V2 | Not used | |||||
TP47 | x | VTT | Not used | |||||
TP48 | x | VTT | Not used | |||||
TP49 | x | VREFA | Not used | |||||
TP50 | x | VREFA | Not used | |||||
TP51 | x | SI_PLL_1V8 | Not used | |||||
TP52 | x | PL_GT_1V35 | Not used | |||||
TP53 | x | PL_GT_1V05 | Not used | |||||
TP54 | x | PL_GT2_1V35 | Not used | |||||
TP55 | x | PL_GT2_1V05 | Not used | |||||
TP56 | x | AVTT_R | Not used | |||||
TP57 | x | AVCC_R | Not used | |||||
TP58 | x | AVTT_L | Not used | |||||
TP59 | x | AVCC_L | Not used | |||||
TP60 | x | AUX_R | Not used | |||||
TP61 | x | AUX_L | Not used | |||||
TP62 | x | PS_1V8 | Not used | |||||
TP63 | x | LP_0V85 | Not used | |||||
TP64 | x | PS_AVTT | Not used | |||||
TP65 | x | PS_AUX | Not used | |||||
TP66 | x | PS_AVCC | Not used | |||||
TP67 | x | U47.7 | Not used | |||||
Chip/Interface | Designator | Connected to | Notes |
|---|---|---|---|
SoC | U1 |
| |
DDR4 SDRAM | U2 / U3 / U9 / U12 |
| |
SPI Flash | U7 / U17 |
| |
EEPROM with MAC | U4 |
| |
Trusted Platform Module 2.0 | U47 |
| |
Programmable Clock Generator | U5 |
| |
Oscillator | U32 |
| 33⅓ MHz |
Oscillator | U25 |
| 25 MHz |
Oscillator quartz | Y1 |
| 25 MHz |
Control signals represent hardware defined logic states, for final state consider firmware and reference designs.
| Signal Name | Connector.Pin | Direction1) | Description |
|---|---|---|---|
| JM2.77 | EN_PLL_PWR | IN | Enable PLL power supply. |
| JM2.79 | EN_GT_L | IN | Enable left GTH transceiver power-up. |
| JM2.80 | PG_PLL_1V8 | OUT | SI_PLL_1V8 power rail powered-up. |
| JM2.81 | PLL_FINC | IN | PLL Frequency incrementation. |
| JM2.82 | PG_PSGT | OUT | GTR transceivers powered-up. |
| JM2.83 | MR | IN | Manual reset. |
| JM2.84 | EN_PSGT | IN | Enable GTR transceiver power-up. |
| JM2.85 | PLL_LOLn | OUT | Loss of lock status. |
| JM2.86 | ERR_STATUS | OUT | PS error status 2). |
| JM2.87 | PLL_SEL1 | IN | PLL clock selection. |
| JM2.88 | ERR_OUT | OUT | PS error indication 2). |
| JM2.89 | PLL_RST | IN | PLL reset. |
| JM2.90 | PLL_SCL | IN | I2C clock. Pulled up to PS_1V8. |
| JM2.91 | PG_GT_R | OUT | Right GTH Transceivers powered-up. |
| JM2.92 | PLL_SDA | IN/OUT | I2C data. Pulled up to PS_1V8. |
| JM2.93 | PLL_SEL0 | IN | PLL clock selection. |
| JM2.94 | PLL_FDEC | IN | PLL Frequency decrementation. |
| JM2.95 | EN_GT_R | IN | Enable right GTH transceiver power-up. |
| JM2.96 | SRST_B | IN | System reset 2). Pulled-up to PS_1V8. |
| JM2.97 | PG_GT_L | OUT | Left GTH Transceivers powered-up. |
| JM2.98 | INIT_B | IN/OUT | Initialisation completion indicator after POR 2). Pulled-up to PS_1V8. |
| JM2.100 | PROG_B | IN/OUT | Power-on reset 2). Pulled-up to PS_1V8. |
| JM2.101 | EN_PL | IN | Enable programmable logic power-up. |
| JM2.102 | EN_FPD | IN | Enable full-power domain power-up. |
| JM2.103 / JM2.105 / JM2.107 / JM2.109 | MODE3..0 | IN | Boot mode selection 2):
Supported Modes depends also on used Carrier. |
| JM2.104 | PG_PL | OUT | Programmable logic powered-up. Pulled-up to PL_DCIN. |
| JM2.106 | LP_GOOD | OUT | Low-power domain powered-up. Pulled up to LP_DCDC. |
| JM2.108 | EN_LPD | IN | Enable low-power domain power-up. |
| JM2.110 | PG_FPD | OUT | Full-power domain powered-up. Pulled-up to DCDCIN. |
| JM2.112 | EN_DDR | IN | Enable DDR power-up. |
| JM2.114 | PG_DDR | OUT | DDR power supply powered-up. Pulled-up to DCDCIN. |
| JM2.116 | DONE | OUT | PS done signal 2). Pulled-up to PS_1V8. |
| JM2.119 / JM2.121 | DX_P / DX_N | - | SoC temperature sensing diode pins 2). |
| JM2.120 / JM2.122 / JM2.124 / JM2.126 | TCK / TDI / TDO / TMS | Signal-dependent | JTAG configuration and debugging interface. JTAG reference voltage: PS_1V8 |
| JM2.125 | PSBATT | IN | PS RTC Battery supply voltage 2) 3). |
| JM2.127 | PUDC_B | IN | Configuration pull-ups setting 2). Pulled-up to PL_1V8. |
| JTAG ( TCK / TDI / TDO / TMS ) | JM2.120 / JM2.122 / JM2.124 / JM2.126 | Signal dependent | |
| MODE3 / MODE2 / MODE1 / MODE0 | JM2.103 / JM2.105 / JM2.107 / JM2.109 | IN | |
| I2C ( PLL_SCL / PLL_SDA) | JM2.90 / JM2.92 | Signal dependent | I2C net with Programmable Clock Generator, EEPROM and TPM 2.0 module. |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
2) See UG1085 for additional information.
3) See Recommended Operating Conditions.
| Power Rail Name/ Schematic Name | Connector.Pin | Direction1) | Notes |
|---|---|---|---|
| DCDCIN | JM2.153 / JM2.154 / JM2.155 / JM2.156 / JM2.157 / JM2.158 / JM2.159 / JM2.160 | IN | Main SoM supply |
| PL_DCIN | JM1.151 / JM1.153 / JM1.155 / JM1.157 / JM1.159 | IN | Programmable logic supply |
| LP_DCDC | JM2.138 / JM2.140 / JM2.142 / JM2.144 | IN | Low power SoC supply |
| GT_DCDC | JM3.157 / JM3.158 / JM3.159 / JM3.160 | IN | MGT transceiver supply |
| PLL_3V3 | JM3.152 | IN | programmable clock generator supply |
| PS_BATT | JM2.125 | IN | Backup voltage supply |
| VCCO_47 | JM3.43 / JM3.44 | IN | IO Supply |
| VCCO_48 | JM3.15 / JM3.16 | IN | IO Supply |
| VCCO_64 | JM4.58 / JM4.106 | IN | IO Supply |
| VREF_64 | JM4.88 | IN | IO reference voltage |
| VCCO_65 | JM4.69 / JM4.105 | IN | IO Supply |
| VREF_65 | JM4.15 | IN | IO reference voltage |
| VCCO_66 | JM1.90 / JM1.120 | IN | IO Supply |
| VREF_66 | JM1.108 | IN | IO reference voltage |
| DDR_1V2 | JM2.135 | OUT | External IO supply |
| SI_PLL_1V8 | JM3.151 | OUT | External IO supply |
PL_1V8 | JM1.91 / JM1.121 | OUT | External IO supply |
| PS_1V8 | JM2.99 / JM3.147 / JM3.148 | OUT | External IO supply |
1) Direction:
The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. GTH transceivers on left and right side are usable independently. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics. Attention: PL usage is not completely independent of PS side. For PL usage it is necessary to enable PS low-power domain.
| Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
|---|---|---|---|---|---|
| 0 | - | - | - | Configuration signal setup. | See Control Signals and Buses. |
| 1 1) | PSBATT | 1.2 V ... 1.5 V | - | Battery connection. | Battery Power Domain usage. When not used, tie to GND. |
| 2 | Processing System (PS): | Procedure for PS starting. | |||
| 2.1 | Low-power domain: | Bring-up for low-power domain PS. | |||
| 2.1.1 | LP_DCDC | 3.3 V (± 5 %) 2) | - | Low-power domain power supply. | Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution. |
| 2.1.2 | EN_LPD | - | - | Low-power domain power enable. | |
| 2.1.3 | LP_GOOD | - | PU 3), LP_DCDC | Low-power domain power good status. | Module power-on sequencing for low-power domain finished. |
| 2.2 | Full-power domain: | Bring-up for full-power domain PS. | Full-power PS domain needs powered low-power PS domain. | ||
| 2.2.1 | DCDCIN | 3.3 V (± 5 %) 2) | Full-power domain and GTR transceiver power supply. | Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution. | |
| 2.2.2 | EN_FPD | DCDCIN | - | Full-power domain power enable. | |
| 2.2.3 | PG_FPD | - | PU 3), DCDCIN | Full-power domain power good status. | Module power-on sequencing for full-power domain finished. |
| 2.2.4 | EN_DDR | DCDCIN | - | DDR memory power enable. | |
| 2.2.5 | PG_DDR | - | PU 3), DCDCIN | DDR memory power good status. | Module power-on sequencing for DDR memory finished. |
2.3 | GTR Transceiver | Procedure for GTR transceiver starting. | PS transceiver usage needs powered PS (low- and full-power domain). | ||
| 2.3.1 | EN_PSGT | DCDCIN | - | GTR transceiver power enable. | |
| 2.3.2 | PG_PSGT | - | - | GTR transceiver power good status. | Module power-on sequencing for GTR transceiver finished. |
| 2 | Programmable Logic (PL) | Procedure for PL starting. | PL usage needs powered PS low-power domain. | ||
| 2.1 | PL_DCIN | 3.3 V (± 5 %) 2) | - | Programmable logic power supply. | Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution. |
| 2.2 | EN_PL | - | PU 3), PL_DCIN | Programmable logic power enable. | |
| 2.3 | PG_PL | - | PU 3), PL_DCIN | Programmable logic power good status. | Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier. |
| 2.4 | VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66 | 4) | - | Module bank voltages. | Enable bank voltages after PG_PL deassertion. |
| 3 | GTH / GTY Transceiver | Procedure for GTH / GTY transceiver starting. | PL transceiver usage needs powered PL and low-power PS domain. | ||
| 3.1 | GT_DCDC | 3.3 V (± 5 %) 2) | - | GTH transceiver power supply. | Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution. |
| 3.21) | EN_PLL_PWR | - | - | PLL power enable. | |
| 3.21) | PG_PLL_1V8 | - | - | PLL power good status. | |
| 3.21) | PLL_3V3 | 3.3 V (± 5 %) | PLL power supply | ||
| 3.3 | EN_GT_L / EN_GT_R | GT_DCDC | - | GTH / GTY left / right transceiver power enable. | Transceivers on left / right side can be used independently. |
| 3.4 | PG_GT_L / PG_GT_R | - | - | GTH / GTY transceiver power good status. | |
| 4 | MR | Manual Reset | Low active release after all needed power domains are enabled. | ||
1) Optional
2) Dependent on the assembly option a higher input voltage may be possible.
3) On module
4) See DS925 for additional information.
5.2 x 7.6 cm UltraSoM+ carrier use four Samtec Razor Beam LP Socket Strip (SS5) on the top side.
When using the standard type on baseboard and module, the mating height is 5 mm.
Other mating heights are possible by using connectors with a different height:
| Order number | REF number | Samtec Number | Type | Contribution to stacking height | Comment |
|---|---|---|---|---|---|
| 27219 | REF192552-01 | SS5-80-3.50-L-D-K-TR | Baseboard connector | 3.5mm | Standard connector used on carrier |
| 27018 | REF-189545-02 | SS5-80-3.00-L-D-K-TR | Baseboard connector | 3 mm | Assembly option on request |
| 27220 | REF-192552-02 | ST5-80-1.50-L-D-P-TR | Module connector | 1.5 mm | Standard connector used on modules |
| 27017 | REF-189545-01 | ST5-80-1.00-L-D-P-TR | Module connector | 1 mm | Assembly option on request |
The module can be manufactured using other connectors upon request.
Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row).
The connector speed rating depends on the stacking height:
Stacking height | Speed rating |
|---|---|
| 4 mm, Single-Ended | 13GHz/26Gbps |
| 4 mm, Differential | 13.5GHz/27Gbps |
| 5 mm, Single-Ended | 13.5GHz/27Gbps |
| 5 mm, Differential | 20GHz/40 Gbps |
The SS5/ST5 series board-to-board spacing is currently available in 4mm (0.157"), 4.5mm (0.177") and 5mm (0.197") stack heights.
The data in the reports is applicable only to the 4mm and 5mm board-to-board mated connector stack height.
| File | Modified | |
|---|---|---|
| PDF File hsc-report-sma_st5-ss5-04mm_web.pdf | May 30, 2017 by Susanne Kunath | |
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| PDF File hsc-report-sma_st5-ss5-05mm_web.pdf | May 30, 2017 by Susanne Kunath | |
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| PDF File REF-192552-01.pdf | Nov 13, 2017 by John Hartfiel | |
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| PDF File REF-192552-02.pdf | Nov 13, 2017 by John Hartfiel | |
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| PDF File ss5.pdf | Nov 13, 2017 by John Hartfiel | |
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| PDF File ss5-st5.pdf | Nov 13, 2017 by John Hartfiel | |
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| PDF File ss5-xx-x.xx-x-d-k-tr-mkt.pdf | Nov 13, 2017 by John Hartfiel | |
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| PDF File st5.pdf | Nov 13, 2017 by John Hartfiel | |
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| PDF File st5-xx-x.xx-x-d-p-tr-mkt.pdf | Nov 13, 2017 by John Hartfiel | |
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| Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
|---|---|---|---|---|
| DCDCIN | Micromodule Power | -0.300 | 6.0 | V |
| PL_DCIN | Micromodule Power | -0.300 | 3.6 | V |
| LP_DCDC | Micromodule Power | -0.300 | 4.0 | V |
| GT_DCDC | Micromodule Power | -0.300 | 6.0 | V |
| PLL_3V3 | PLL power supply | -0.500 | 3.8 | V |
| PS_BATT | RTC / BBRAM | -0.500 | 2.000 | V |
| VCCO_47 | HD IO Bank power supply | -0.500 | 3.400 | V |
| VCCO_48 | HD IO Bank power supply | -0.500 | 3.400 | V |
| VCCO_64 | HP IO Bank power supply | -0.500 | 2.000 | V |
VCCO_65 | HP IO Bank power supply | -0.500 | 2.000 | V |
| VCCO_66 | HP IO Bank power supply | -0.500 | 2.000 | V |
| VREF_64 | Bank input reference voltage | -0.500 | 2.000 | V |
| VREF_65 | Bank input reference voltage | -0.500 | 2.000 | V |
| VREF_66 | Bank input reference voltage | -0.500 | 2.000 | V |
*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.
The categories are:
These categories do not take into account the entire custom system consisting of:
Classification of the module can be looked up here: Article Number Information i.e.: TExxxx-xx-xx'I'xx, the 'I' indicates that all components are at least in Industrial temperature class.
The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.
The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| DCDCIN 1) | 3.1 | 5.5 | V | See SoM data-sheet. |
| PL_DCIN 1) | 2.5 | 5.5 | V | See SoM data-sheet. |
| LP_DCDC 1) | 3.1 | 3.6 | V | See SoM data-sheet. |
| GT_DCDC 1) | 3.1 | 5.5 | V | See SoM data-sheet. |
| PLL_3V3 | 3.14 | 3.46 | V | See SoM data-sheet. |
| PS_BATT | 1.20 | 1.50 | V | See SoM data-sheet. |
| VCCO_47 | 1.14 | 3.40 | V | See SoM data-sheet. |
| VCCO_48 | 1.14 | 3.40 | V | See SoM data-sheet. |
| VCCO_64 | 0.95 | 1.90 | V | See SoM data-sheet. |
VCCO_65 | 0.95 | 1.90 | V | See SoM data-sheet. |
| VCCO_66 | 0.95 | 1.90 | V | See SoM data-sheet. |
| VREF_64 | 0.6 | 1.2 | V | See SoM data-sheet. |
| VREF_65 | 0.6 | 1.2 | V | See SoM data-sheet. |
| VREF_66 | 0.6 | 1.2 | V | See SoM data-sheet. |
Module size: 52.0 mm × 76.0 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm.
| Trenz shop TE0808 overview page* | |
|---|---|
| English page | German page |
*) Module article name encoding table: Zynq Ultrascale+ based modules (MPSoC, RFSoC)
The hardware revision number can be found on the PCB board together with the module's model number, separated by a dash.
| Date | Revision | Changes | Documentation Link |
|---|---|---|---|
| 2026-03 | 06 |
| |
| 2020-04 | 05 |
29.11.2022 9. Changed note near J2.97 and net PG_GT_L from "On board pull-up R" to "External pull-up R Required" 30.04.2025 10. MT: L1-L5, L7 (obsolete) changed to MPZ0603S121HT000 | |
| - | 04A |
| |
| - | 04 |
| |
| - | 03 | - | REV03 |
| - | 02 | - | REV02 |
| - | 01 |
|
| Date | Revision | Contributors | Description |
|---|---|---|---|
| |||
| 2026-06-19 | v.53 | Kilian Jahn |
|
2024-09-24 | v.50 | John Hartfiel |
|
2024-09-18 | v.48 | John Hartfiel |
|
2023-10-13 | v.44 | ED |
|
2022-09-13 | v.41 | Vadim Yunitski |
|
| 2021-09-07 | V.39 | John Hartfiel |
|
| 2021-05-17 | v.37 | John Hartfiel |
|
| 2021-03-11 | v.35 | Antti Lukats |
|
2019-01-27 | v.30 | Martin Rohrmüller |
|
2018-11-20 | v.29 | John Hartfiel |
|
2018-08-27 | v.27 | John Hartfiel |
|
2028-06-28 | v.26 | John Hartfiel |
|
2017-11-13 | v.24 | Ali Naseri |
|
2017-11-13 | v.22 | John Hartfiel |
|
| 2017-10-20 | v.21 | Ali Naseri |
|
| 2017-08-28 | v.15 | John Hartfiel |
|
| 2017-08-28 | v.14 | Jan Kumann |
|
| 2017-08-15 | v.12 | Vitali Tsiukala |
|
| 2017-08-15 | v.11 | John Hartfiel, Ali Naseri |
|
| 2017-02-06 | v.1 | Jan Kumann |
|
-- | all |
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Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.
Products (incl. Software and Firmware) are exclusively designed, manufactured, and distributed for industrial applications. They are not intended, authorized, or certified for use in critical safety applications, medical devices, aerospace, nuclear, life-support, traffic-control, military, or other environments where malfunction or failure could result in personal injury, death, or significant property or environmental damage.
Trenz Electronic GmbH (“Manufacturer”) excludes any liability for inappropriate use in such contexts. The Customer bears all responsibility for verifying suitability and compliance with applicable regulations when deploying in any critical-use scenario. The Customer also agrees to indemnify and hold harmless the Manufacturer from any third-party claims or liabilities arising from such use.
No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.
REACH
Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
RoHS
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.