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The Trenz Electronic TE0955 is an AMD Versal AI Edge SoC based System on Module (SoM).
The SoC combines a dual core Arm Cortex-A72 Application Processor, a dual core Arm Cortex-R5F Real Time Processor, a FPGA and an AI Engine Machine Learning (AIE-ML).
The module integrates the SoC's two Quad GTYP transceivers, DDR4LP SDRAM, SPI Flash memory for configuration and operation, a Gigabit Ethernet PHY, a USB 2.0 PHY and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged B2B connectors.
Refer to http://trenz.org/te0955-info for current online available documentation.
SoC
RAM/Storage
On Board
Interface
Power
Dimension
40 mm x 56.4 mm
Notes
1) Available as assembly variant or upon request.
2) Other sizes/devices, which are pin/package-compatible, upon request.
Storage device name | Content | Notes |
|---|---|---|
Octal SPI Flash, U34 | Not programmed | |
e.MMC, U2 | Not programmed | |
EEPROM, U17 | Manufacturer programmed MAC | |
LPDDR4 SDRAM, U35, U36 | Not programmed |
Connector Type | Designator | Interface | IO count | Notes |
|---|---|---|---|---|
| B2B | JM5 | IO HP | 54x SE / 27x DIFF | Bank 703 |
| B2B | JM5 | MGT | 8x GTYP | Banks 103 & 104 |
| B2B | JM5 | MGT CLK | 4x GTYP CLK | Banks 103 & 104 |
| B2B | JM6 | IO HD | 22x SE / 11x DIFF | Bank 302 |
| B2B | JM6 | ETH MDI | 8x DIFF | Bank 502 |
| B2B | JM6 | ETH PHY LED | 2x SE | Bank 502 |
| B2B | JM6 | SDIO | 11x SE | Bank 501 |
| B2B | JM6 | GPIO | 4x SE | Bank 501 & 502 |
| B2B | JM6 | USB 2.0 | 1x DIFF | Bank 500 |
Test Point | REV02 | REV01 Signal | |||
|---|---|---|---|---|---|
Top | Bottom | Notes | Signal | ||
TP1 | x | 3V3_AO | |||
TP2 | x | DDR_1V1 | |||
TP3 | x | 3V3_AO | |||
TP4 | x | DDR_1V1 | |||
TP5 | x | 3V3 | |||
TP6 | x | 3V3 | |||
TP7 | x | 1V8 | |||
TP8 | x | 1V8 | |||
TP9 | x | OM_SCL | |||
TP10 | x | TDI | |||
TP11 | x | OM_SDA | |||
TP12 | x | TDO | |||
TP13 | x | GND | |||
TP14 | x | TCK | |||
TP15 | x | TMS | |||
TP16 | x | V_IO_CFG | |||
TP17 | x | GND | |||
TP18 | x | V_VCC_CORE | |||
TP19 | x | V_VCC_CORE | |||
TP20 | x | V_FUSE | |||
TP21 | x | V_VCC_SOC | |||
TP22 | x | V_VCC_SOC | |||
TP23 | x | V_VCCAUX | |||
TP24 | x | V_VCCAUX | |||
TP25 | x | GTYP_AVCC | |||
TP26 | x | GTYP_AVCC | |||
TP27 | x | GTYP_AVCC_AUX | |||
TP28 | x | GTYP_AVCC_AUX | |||
TP29 | x | PG_ALL | |||
TP30 | x | GTYP_AVTT | |||
TP31 | x | GTYP_AVTT | |||
TP32 | x | TPM_PP | Not used | ||
Chip/Interface | Designator | Connected To | Notes |
|---|---|---|---|
SoC | U1 |
| |
LPDDR4 | U35, U36 |
| |
OSPI | U34 |
| |
eMMC | U2 |
| |
Ethernet PHY | U3 |
| Supports TSN, PTP |
OPTIGA™ Trust M Security Element | U14 |
| |
CryptoAuthentication™ Device | U15 |
| |
Trusted Platform Module | U37 |
| |
EEPROM with MAC | U17 |
| |
USB PHY | U5 |
| |
Chrystal | Y1 |
| Default assembly 32.768 kHz. |
Oscillator | U24 |
| Default assembly 33⅓ MHz. |
Oscillator | U27 |
| REF CLK for Memory controller. Default assembly 200 MHz. |
Oscillator | U28 |
| User PL clock Default assembly 200 MHz. |
| Oscillator | U4 |
| Default assembly 25 MHz. |
| Oscillator | U6 |
| Default assembly 24 MHz. |
Signal Name | Connector.Pin | Direction | Description |
|---|---|---|---|
JTAG( TDI / TCK / TDO / TMS ) | JM6.D51 / JM6.D52 / JM6.D54 / JM6.D55 | Signal dependent | SoC JTAG. |
UART0_RX / UART0_TX | JM6.B49 / JM6.B50 | Signal dependent | Software implementation dependent. Alternative GPIO/I2C1_SCL/CAN_FD_1_TX (no pull-up at SoM). |
UART1_RX / UART1_TX | JM6.A49 / JM6.50 | Signal dependent | Software implementation dependent. Alternative GPIO/I2C1_SDA/CAN_FD_1_RX (no pull-up at SoM). |
I2C( M_INT# / M_SCL / M_SDA ) | JM6.C49 / JM6.C50 / JM6.C51 | Signal dependent | Software implementation dependent. |
I2C( U_SCL / U_SDA / U_INT# ) | JM6.D33 / JM6.D34 / JM6.D35 | Signal dependent | Software implementation dependent. |
USB0_ID / USB0_CPEN / V_USB0 | JM6.47 / JM6.C48 / JM6.D46 | Signal dependent | Software implementation dependent. |
PERST0# / PERST1# | JM6.B51 / JM6.B52 | INOUT | Intended for use as PCIe reset signal from PL or PS side of the SoC. Can be used as IO pin. |
PWR_EN | JM6.D58 | IN | Enable SoM Power Rails. |
PWR_EN_IO | JM6.D59 | OUT | Signals to carrier to enable the IO Voltage Rails. |
ERROR_R 2) | JM6.A39 | OUT | The ERROR_OUT pin is an output-only, open-drain signal with a weak internal pull-up and an external pull-up. When an error occurs in the device, the ERROR_OUT signal is put in a High-Z state and pulled High. The specific errors that cause this pin to assert can be determined and programmed by software. |
RST_CPU# | JM6.C58 | INOUT | Option; connectable to GPIO0 |
RST_SYS# 2) | JM6.C59 | IN | Signals to carrier Power Good of all voltage converters. Acts as external SoM reset signal when pulled low. |
RST_M2C# | JM6.B58 | OUT | Signals to carrier a SoM reset event occurs. SoM reset signal for OSPI, e.MMC and Ethernet. Also connected to SoC RST# signal. Option; connectable to GPIO3_LS. |
MODE0 / MODE1 / MODE2 / MODE3 2) | JM6.C54 / Jm6.C55 / JM6.C56 / JM6.C57 | IN | The MODE[3:0] pins are used to select the boot mode for the device. The value of these pins is captured on the rising edge of POR_B. See Boot Modes and Interfaces for available boot mode details. |
DONE 2) | JM6.C53 | OUT | The DONE pin is an output-only, open-drain signal with a weak internal pull-up. An external pull-up is recommended. DONE is controlled by the DONE register. After POR, the DONE signal is Low. When the PLM successfully completes the boot sequence, the software sets the [DONE] bit High, which causes the output buffer to float and be pulled High externally. |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
2) See Introduction to Versal Adaptive SoCs for further insights.
Power Rail Name / Schematic Name | Connector.Pin | Direction1) | Notes |
|---|---|---|---|
V_MOD1 | JM5.A7 / JM5.A15 / JM5.A47 / JM5.A55 / JM5.B5 / JM5.B11 / JM5.B17 / JM5.B45 / JM5.B51 / JM5.B57 / JM6.C5 / JM6.C11 / JM6.C17 / JM6.D7 / JM6.D15 | IN | |
V_IO_CFG | JM6.C52 | IN | |
V_IO_W01 | JM5.D3 / JM5.D17 | IN | |
V_IO_X3 | JM6.B59 | IN | |
V_BAT | JM6.A59 | IN | |
1V8 | JM5.C7 / JM5.C15 / JM6.B7 / JM6.B15 | OUT | |
3V3_AO | JM6.B59 | OUT |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
|---|---|---|---|---|---|
| 0 | - | - | - | Configuration signal setup. | |
| 1 | V_MOD1 | 5 V to 12 V | - | Apply power to the SoM. | |
| 2 | PWR_EN | - | Pull-up 3.3 V | Enable power to peripheral SoM devices. | |
| 3 | PWR_EN_IO | - | Pull-up 3.3 V | When high, apply IO Bank Voltages. | |
| 4 | V_IO_CFG V_IO_W01 V_IO_X3 | 1.71 V to 1.89 V 0.95 V to 1.57 V 1.71 V to 3.399 V | - | Connect IO Bank Voltage power supply. |
The carriers use Samtec AcceleRate HD High-Density on top side.
When using the same type on baseboard, the mating height is 5 mm. Other mating heights are possible by using connectors with a different height:
| Order number | REF number | Samtec Number | Type | Contribution to stacking height | Comment |
|---|---|---|---|---|---|
| 30095 | REF-30095 | ADM6-60-01.5-L-4-2 | Module connector | 1.5 mm | Standard connector used on modules (legacy) |
| - | - | ADM6-60-01.5-L-4-0 | Module connector | 1.5 mm | Alternative connector |
| 31137 | REF-31137 | ADF6-60-03.5-L-4-2 | Baseboard connector | 3.5 mm | Standard connector used on carrier (legacy) |
| - | - | ADF6-60-03.5-L-4-0 | Baseboard connector | 3.5 mm | Alternative connector |
The module can be manufactured using other connectors upon request.
The AcceleRate HD High-Density connector speed rating depends on the stacking height; please see the following table:
| Connector | Stacking height | Speed rating |
|---|---|---|
| ADM6-XX-XX.X-X-X-2 | 5 mm | 56 Gbps |
| ADM6-XX-XX.X-X-X-0 | 5 mm | 64 Gbps |
Current rating of Samtec AcceleRate HD High-Density B2B connectors is 1.34 A per pin (4 pins powered).
| File | Modified | |
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| PDF File 20200225_hsc_adm6-xx-01p5-xxx-4-a_adf6-xx-03p5-xxx-4-a.pdf | Mar 04, 2022 by ED | |
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| PDF File adf6.pdf | Mar 04, 2022 by ED | |
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| PDF File adm6.pdf | Mar 04, 2022 by ED | |
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| PDF File adm6-xxx-xx.x-xxx-4-x-x-xr-mkt.pdf | Mar 04, 2022 by ED | |
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| PDF File adm6-xxx-xx.x-xxx-x-x-x-footprint.pdf | Mar 04, 2022 by ED | |
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| PDF File Updated - 20200225_hsc_adm6-xx-01p5-xxx-4-a_adf6-xx-03p5-xxx-4-a.pdf | Jun 18, 2026 by Kilian Jahn | |
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| PDF File Updated - adm6.pdf | Jun 18, 2026 by Kilian Jahn | |
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| PDF File Updated - adm6-xxx-xx.x-xxx-x-x-x-footprint.pdf | Jun 18, 2026 by Kilian Jahn | |
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| PDF File Updated - adx6.pdf | Jun 18, 2026 by Kilian Jahn | |
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| PDF File Updated - adx6 mated document-mkt.pdf | Jun 18, 2026 by Kilian Jahn | |
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Power Rail / Schematic Name | Description | Min | Max | Unit |
|---|---|---|---|---|
V_MOD1 | SoM power supply | -0.3 | 18 | V |
V_IO_CFG | SoC Configuration Bank power supply | 0 | 3.6 | V |
V_IO_W01 | SoC IO Bank 703 power supply | -0.3 | 1.65 | V |
V_IO_X3 | SoC IO Bank 302 power supply | -0.3 | 3.63 | V |
V_BAT | Backup power supply | -0.5 | 3.63 | V |
*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.
The categories are:
These categories do not take into account the entire custom system consisting of:
Classification of the module can be locked up here: Article Number Information i.e.: TExxxx-xx-xx'I'xx, the 'I' indicates that all components are at least in Industrial temperature class.
The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.
Parameter | Min | Max | Unit | Reference Document |
|---|---|---|---|---|
V_MOD1 | 4.75 | 12.6 | V | See schematic. |
V_IO_CFG | 1.71 | 1.89 | V | See schematic. |
V_IO_W01 | 0.95 | 1.575 | V | See schematic. |
V_IO_X3 | 1.71 | 3.399 | V | See schematic. |
V_BAT | 1.215 | 1.485 | V | See schematic. |
V1V8 | 1.71 | 1.89 | V | See schematic. |
3V3_AO | 3.201 | 3.399 | V | See schematic. |
Module size: 40 × 56.4 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm
All dimensions are shown in millimeters.
Trenz shop TE0955 overview page* | |
|---|---|
*) Module article name encoding table: AMD Versal based modules
The hardware revision number is located on the PCB next to the module identifier, separated by a dash.
Date | Revision | Changes | Documentation Link |
|---|---|---|---|
2025-12 | REV02 | 1. Set R156 to assembled and connected to GTYP_AVCC_AUX rail instead of 1V8. Removed patch including R156_NEW. | |
2025-02 | REV01 | Initial release |
Date | Revision | Contributor | Description |
|---|---|---|---|
| |||
2026-01-23 | v.6 | Martin Rohrmüller |
|
v.4 | Martin Rohrmüller |
| |
v.2 | Kilian Jahn |
| |
-- | all |
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