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Overview

The Trenz Electronic TE0820 is an industrial/extended 4 x 5 SoM integrating an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM, eMMC memory, flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. The module is equipped with a Lattice Mach XO2 CPLD for system controlling. Three high-speed connectors provide a large number of inputs and outputs. Additionally, the module provides Gigabit Ethernet and USB 2.0 transceivers.

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All components cover at least the industrial temperature range. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.

Refer to http://trenz.org/te0820-info for the current online version of this manual and other available documentation.


Key Features


  • SoC
    • Device: ZU1 / ZU2 / ZU3 / ZU4 / ZU5 1)
    • Engine:  CG / EG / EV 1)
    • Speedgrade: -1 / -1L / -2 / -2L / 3 1)
    • Temperature Range: Extended / Industrial 1)
    • Package: SFVC784
  • RAM/Storage
    • 2 GByte DDR4 SDRAM 2)
    • 2 x 64 MByte Serial Flash 3)
    • 8 GByte eMMC 3)
    • EEPROM with MAC address
  • On Board
    • Lattice MachXO2 CPLD
    • Programmable Clock Generator
    • Hi-speed USB2 ULPI Transceiver
    • 10/100/1000 Mbps Ethernet Transceiver
    • 4x LEDS
  • Interface
    • 3 x B2B Connector (LSHM)
      • up to 132 PL HP IO
      • up to PS 14 MIO
      • 4 PS GTR
      • ETH (MDI) or SGMII
      • USB
      • SDIO
      • CFG, JTAG
  • Power
    • 3.3 V power supply via B2B Connector needed 4).
  • Dimension
    • 40 mm x 50 mm
  • Notes
    1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
    2) Up to 4 GByte are possible with a maximum bandwidth of 2400 MBit/s.
    3) Please, take care of the possible assembly options.
    4) Higher input voltage may be possible.

Block Diagram



TE0820-03 block diagram

Main Components

TE0820 main components
  1. AMD Zynq UltraScale+ MPSoC, U1
  2. QSPI flash memory, U7, U17
  3. DDR4 SDRAM, U2, U3
  4. eMMC memory, U6
  5. EEPROM, U25
  6. Ethernet transceiver, U8
  7. USB 2.0 ULPI transceiver, U18
  8. B2B Connector, JM1, JM2, JM3
  9. Lattice Semiconductor MachXO2 System Controller CPLD, U21
  10. Clock generator, U10
  11. Oscillator, U11, U14, U32
  12. Done LED, D1
  13. User LED, D2
  14. Error Out LED, D3
  15. Error Status LED, D4

Initial Delivery State


Storage device name

Content

Notes

Quad SPI Flash

not programmed


eMMC

not programmed


DDR4 SDRAM

not programmed


Programmable Clock Generator

not programmed


EEPROM

not programmed besides factory programmed MAC address


System Controller CPLD

programmedTE0820 CPLD
Initial delivery state of programmable devices on the module


Signals, Interfaces and Pins

Connectors

Connector TypeDesignatorInterfaceIO CNTNotes
B2BJM1 ETH  - MDIETH
B2BJM1HP 48 SE / 24 DIFF 
B2BJM1 MIO  8 x GPIO
B2BJM1 SDIO SDIO or 6 x MIO 
B2BJM2 HP  68 SE / 33 DIFF
B2BJM2CFGJTAG
B2BJM3ETHSGMII
B2BJM3MGT PS4 x MGT (RX/TX)
B2BJM3MGT PSMGT CLK
B2BJM3CLKDIFF CLK
B2BJM3HP 16 SE / 8 DIFF
B2BJM3USBUSB
Board Connectors


Test Points 


Test PointSignalNotes1)
TP1PS_LP0V85
TP2DDR_2V5
TP3PS_AVCC
TP4DDR_1V2
TP5PS_AVTT
TP6VTT
TP7PS_FP0V85
TP8VREFA
TP9DDR4-TENpulled-down to GND
TP10PS_PLL
TP11PL_VCCINT
TP12PG_ALLpulled-up to 3.3VIN
TP15PL_VCCINT_IO
TP16PL_VCU

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Test Points Information


On-board Peripherals


Chip/InterfaceDesignatorConnected ToNotes

QSPI Flash

U7, U17SoC - PS

EEPROM

U25SoC - PS

DDR4 SDRAM

U2, U3SoC - PS

GigaBit Ethernet

U8SoC - PS, B2B

USB2.0 Transceiver

U18SoC - PS, B2B

eMMC Memory

U6SoC - PS

Oscillator

U32SoC - PS
OscillatorU14USB PHY
OscillatorU11Clock Generator, ETH PHY

Programmable Clock Generator

U10SoC - PS, B2B

CPLD

U21SoC - PS, B2B

LED

D1SoC - PSRed, Done LED (see U+ Zynq TRM)
LEDD2CPLDGreen, Status LED (see TE0820 CPLD)
LEDD3SoC - PSRed, PS Error LED (see U+ Zynq TRM)
LEDD4SoC - PSGreen, PS Error Status LED (see U+ Zynq TRM)
On board peripherals



Configuration and System Control Signals


Connector+Pin

Signal Name

Direction1)Description
JM1-7NOSEQIN/OUTSee 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM1-28EN1INSee 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM1-30PGOODIN/OUTSee 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM1-32MODEINSee 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM1-89JTAGENINSee 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM2-18RESININReset signal, see 4 x 5 SoM Integration Guide.
JM2-93 / JM2-95 / JM2-97 / JM2-99TMS / TDI / TDO / TCKSignal-dependent

JTAG configuration and debugging interface.

JTAG reference voltage: 3.3VIN

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Controller signal.


Power and Power-On Sequence


Power Rails

Power Rail Name/ Schematic NameConnector.PinDirection1)Notes
VINJM1.1 / JM1.3 / JM1.5 / JM2.2 / JM2.4 / JM2.6 / JM2.8INSupply voltage from carrier board
3.3VINJM1.13 / JM1.15INSupply voltage from carrier board
3.3VINJM2.91OUTJTAG reference voltage

+3.3V

JM2.10 / JM2.12OUTInternal +3.3 V voltage level

+1.8V

JM1.39OUTInternal +1.8V voltage level

VCCO_64

JM2.7 / JM2.9INHP Bank voltage (max. +1.9 V)

VCCO_65

JM2.5INHP Bank voltage (max. +1.9 V)
VCCO_66JM1.9 / JM1.11INHP Bank voltage (max. +1.9 V)

PSBATT

JM1.79INPS battery supply voltage

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Module power rails.

Recommended Power up Sequencing



SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes
0---Configuration signal setup.See Configuration and System Control Signals.
1 1)3.3VIN3.3 V (± 5 %)-Management and SoC power supply.Main module power supply for management and SoC. 1 A recommended. Power consumption depends mainly on design and cooling solution.
2 1)VIN

3.3 V (± 5 %) 2)

       OR

5.0 V (± 5 %) 2)

-Main module power supply.Main module power supply for management and SoC. 3 A to 7 A recommended. Power consumption depends mainly on design and cooling solution.
31.8V--1.8 V on-module power supply.
43.3V--3.3 V on-module power supply.
5VCCO_64 / VCCO_65 / VCCO_66 2)-Module bank voltages.Enable bank voltages after 1.8 V and/or 3.3 V are available on carrier.

1) In cases where VIN = 3.3VIN = 3.3 V, both voltages can be enabled together.

2) A higher or lower input voltage may be possible. 

2) See DS925 for additional information.

Baseboard Design Hints


Board to Board Connectors 

 

These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.

4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.

  • 2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
  • 1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)
Connector Mating height

When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height

Order numberConnector on baseboardcompatible toMating height
23836REF-189016-01LSHM-150-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-150-03.0-L-DV-A-S-K-TRLSHM-150-03.0-L-DV-A-S-K-TR7.0 mm
23838REF-189016-02LSHM-150-04.0-L-DV-A-S-K-TR8.0 mm

LSHM-150-06.0-L-DV-A-S-K-TRLSHM-150-06.0-L-DV-A-S-K-TR10.0mm
26125REF-189017-01LSHM-130-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-130-03.0-L-DV-A-S-K-TRLSHM-130-03.0-L-DV-A-S-K-TR7.0 mm
24903 REF-189017-02LSHM-130-04.0-L-DV-A-S-K-TR8.0 mm

LSHM-130-06.0-L-DV-A-S-K-TRLSHM-130-06.0-L-DV-A-S-K-TR10.0mm
Connectors.

The module can be manufactured using other connectors upon request.

Connector Speed Ratings

The LSHM connector speed rating depends on the stacking height; please see the following table:

Stacking heightSpeed rating
12 mm, Single-Ended7.5 GHz / 15 Gbps
12 mm, Differential

6.5 GHz / 13 Gbps

5 mm, Single-Ended11.5 GHz / 23 Gbps
5 mm, Differential7.0 GHz / 14 Gbps
Speed rating.
Current Rating

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Connector Mechanical Ratings
  • Shock: 100G, 6 ms Sine
  • Vibration: 7.5G random, 2 hours per axis, 3 axes total


Manufacturer Documentation

  File Modified
PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report 07 04, 2016 by Thorsten Trenz
PDF File lshm_dv.pdf LSHM catalog page 07 04, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing 07 04, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189016-01.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189016-02.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189017-01.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189017-02.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report 07 04, 2016 by Thorsten Trenz
PDF File tc0929--2611_qua(1).pdf Shock and vibration report 07 04, 2016 by Thorsten Trenz



Technical Specifications 

  

Absolute Maximum Ratings *)

Power Rail Name/ Schematic NameDescriptionMinMaxUnit
VINSupply voltage-0.37V
3.3VINSupply voltage-0.33.75V

VCCO_64

I/O bank voltage-0.52.0V

VCCO_65

I/O bank voltage-0.52.0V
VCCO_66I/O bank voltage-0.52.0V

PSBATT

RTC / BBRAM-0.52.0V
Absolute maximum ratings

 *) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
   or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version.  Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

  • Variants of modules are described here: Article Number Information
  • Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
  • Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C


ParameterMinMaxUnitsReference Document
VIN 1)

3.135

OR

4.75

3.465

OR

5.25

V


V


3.3VIN3.1353.465V

VCCO_64

0.9501.900VSee FPGA datasheet.

VCCO_65

0.9501.900VSee FPGA datasheet.
VCCO_660.9501.900VSee FPGA datasheet.

PSBATT

1.2001.500VSee FPGA datasheet.

1) Higher values may possible. For more information consult schematic and according datasheets.

Recommended operating conditions.


Physical Dimensions

  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm.

PCB thickness: 1.66 mm (± 10 %).



Physical Dimension


Currently Offered Variants 

  

Trenz shop TE0820 overview page
English pageGerman page
Trenz Electronic Shop Overview


Revision History

Hardware Revision History


Figure 6: Module hardware revision number
 


DateRevisionChangesDocumentation Link
2022-06-2205
  • Changed EOL ferrite beads L1..5,L7,L9..12.
  • Changed EOL DCDC U5 (EN6363QI -> MPM3860GQW-Z).
  • Changed EOL load switch U28 (TPS27082LDDCR -> MP5077GG-Z ).
  • Added additional decoupling capacitors and changed caps 4.7uF to 10uF (AMD doc UG583 v1.23).
  • Added pull-down and testpoint to TEN DDR4 signal.
  • Changed EOL transistor T1 (AO7800 -> BSD840NH6327XTSA1).
  • Added voltage detector U30 (BD39040MUF-CE2).
  • Changed EOL eMMC U6 (MTFC4GACAJCN-4M -> SDINBDG4-8G-XI2).
  • Changed EOL MEMS U14 (SiT8008AI-73-XXS-52.000000E -> SiT8008BI-73-XXS-52.000000E).
  • Added signal PG_ALL (U30) to CPLD (pin5).
  • Added option (depends assembly variants, for all assembly variants R128 set as populated, instead special inquiry) signal POR_B through R128, T2 to CPLD (pin27).
  • Added option (depends assembly variants, for all assembly variants R95 set as DNP, instead special inquiry) signal EN1 through R95 to DCDC U5.
  • Added option (depends assembly variants, for all assembly variants U29 and R129 set as populated, instead special inquiry) signal PHY_LED1 through level translator U29 to FPGA (U1.K7).
  • Added resistors R130 & R131 (select Power-on delay override, for all assembly variants R130 set as DNP -> Standard PL Power-on delay time).
  • Added diode D5.
  • Added Power Diagram sheet.
  • LIB components update.
TE0820-05
2020-08-1404
  • Fixed DDR4 connection (BG1), support B-die DDR4 Industrial grade chips.
  • Added R93, changed value C62, change obsolete U28.
  • Added R89 (10R).
  • Added additional caps 4.7uF to PS_AVTT/PS_AVCC (AMD doc UG583).
  • Changed R51 20k ->10K (PS_AVCC = 0.85V, AMD doc DS925 v1.17).
  • Fixed DDR4 connection (Alert).
  • Added 3.3V signal to CPLD.
  • Added testpoints.
  • LIB components update.
TE0820-04
2019-01-0203
  • Fixed VCU connection: add additional DCDC (0.9V).
  • LIB components update.
  • Change package 1K resistors (0402 -> 0201).
  • Added LEDs (1x user LED, 1x LED for ERR_STATUS, 1xLED for ERR_OUT).
  • Change obsolete 2xSPI Flash (256MBit) -> 2xSPI Flash (512MBit).
  • Added additional DCDCs (PL_VCCINT_IO, PS_FP0V85).
  • Changed DCDC (U5) 6A (optional 4A).
TE0820-03
2017-08-1702
  • Added MAC EEPROM (slave address).
  • LIB components update.
  • Fixed SD Card connection.
  • Fixed sense connection from DCDC.
  • Made correct power connection for VCU (removed DCDC, added resistors and caps like as AMD recommended).
  • Added resistors for variants (ZU+ with/without VCU).
  • Added termination resistors (240R) to VRP pins fro all HP-banks.
TE0820-02
2016-12-2301PrototypeTE0820-01
Hardware Revision History

 Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History



DateRevisionContributorDescription

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  • Updated to new TRM style
  • Updated for REV05

2022-11-02

v.100

John Hartfiel

  • Corrected Key features
2021-12-17v.99Vadim Yunitski
  • Corrected 'Bank voltages' table 
2021-07-14v.98John Hartfiel
  • bugfix boot mode
2021-07-05v.97John Hartfiel
  • published
  • style changes
2020-09-18v.95Pedram Babakhani
  • Update to REV04
  • Update the TRM format
  • Technical Information update
2020-03-16v.87John Hartfiel
  • Corrected PLL section
  • Corrected Designators USB, ETH PHY, CLK section
2020-02-03v.85Martin Rohrmüller
  • Corrected #MIOs for QSPI and USB in block diagram
2019-11-28v.81Martin Rohrmüller
  • typo and designator in section USB interface corrected
2019-10-30v.80John Hartfiel
  • typo correction
2019-09-17v79Martin Rohrmüller
  • Updated according to PCN-20190110: eMMC, QSPI-Flash

2019-07-17

v.78Martin Rohrmüller
  • Corrected PJTAG Mio Pin29 in table 8

2019-05-08

v.77John Hartfiel
  • Corrected EEPROM I2C Address
  • Correction USB PHY connection

2018-11-12

v.74

John Hartfiel
  • update boot section

2018-08-30

v.73John Hartfiel
  • typo correction
  • update CPLD section
  • add LEDs to component list
  • add 3D picture of REV03 instead of REV01 picture

2018-07-12

v.69Ali Naseri
  • Update PCB Rev03

2018-06-11

v.61John Hartfiel
  • Rework chapter currently available products
  • add PJTAG note to MIOtable
2018-03-12v.54
  • Correction Power Rail Section
2017-11-20v.51John Hartfiel
  • Correction Default MIO Configuration Table
2017-11-10v.50John Hartfiel
  • Replace B2B connector section
2017-10-18v.49John Hartfiel
  • add eMMC section
2017-09-25v.48John Hartfiel
  • Correction in the "Board to Board (B2B) I/Os" section
  • Update in the "Variants Currently In Production" section
2017-09-18v.47John Hartfiel
  • Update PS MIO table
2017-08-30v.46Jan Kumann
  • MGT lanes section added.

2017-08-24

v.36

John Hartfiel
  • Correction in the  "Key Features" section.
2017-08-21v.34John Hartfiel
  • "Initial delivery state" section updated.
2017-08-21v.33Jan Kumann
  • HW revision 02 block diagram added.
  • Power distribution and power-on sequence diagram added.
  • System Controller CPLD and DDR4 SDRAM sections added.
  • TRM update to the template revision 1.6
  • Weight section removed.
  • Few minor corrections.



2017-08-18


v.7

John Hartfiel
  • Style changes
  • Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
  • Correction of MIO SD Pin-out, System Controller chapter
  • Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

  • Initial version

--

all

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  • --
Document change history.


Disclaimer

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


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