TE0820 TRM

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Overview

The Trenz Electronic TE0820 is an industrial-grade 4 x 5 cm MPSoC SoM (System on Module) module integrating a Xilinx Zynq UltraScale+ with up to 4 GByte 32-Bit DDR4 SDRAM, max. 128 MByte SPI Boot Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.

Key Features

• Xilinx Zynq UltraScale+ MPSoC (XCZU2CG / XCZU2EG, XCZU3CG / XCZU3EG or XCZU4CG / XCZU4EV)
  • Quad-core or dual-core Cortex-A53 64-bit ARM v8 application processing unit (APU) (depends on assembly variant CG,EG,EV)
  • Dual Cortex-R5 32-bit ARM v7 real-time processing unit (RPU)

  • Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:

    • PCI Express® interface version 2.1 compliant
    • SATA 3.1 specification compliant interface

    • DisplayPort source-only interface with video resolution up to 4k x 2k

    • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
    • 1 GB/s serial GMII interface
  • 132 x HP PL I/Os (3 banks)
  • 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
  • 4 x serial PS GTR transceivers
• 2 GByte DDR4 SDRAM, 32bit databus-width
• 128 MByte QSPI boot Flash in dual parallel mode
• 4 GByte eMMC
• Programmable quad PLL clock generator PLL for PS GTR clocks (optional external reference)
• Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
• MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
• Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  
• Plug-on module with 2 x 100-pin and 1 x 60-pin high-speed hermaphroditic strips
• All power supplies on board
• Size: 50 x 40 mm

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Main Components

1. Xilinx Zynq UltraScale+ MPSoC, U1
2. 1.8V, 512 Mbit QSPI flash memory, U7
3. 1.8V, 512 Mbit QSPI flash memory, U17
4. 8 Gbit (512 x 16) DDR4 SDRAM, U2
5. 8 Gbit (512 x 16) DDR4 SDRAM, U3
6. Marvell Alaska 88E1512 integrated 10/100/1000 Mbps energy efficient ethernet transceiver, U8
7. 6A PowerSoC DC-DC converter (PL_VCCINT, 0.85V), U5
8. B2B connector Samtec Razor Beam™ LSHM-150, JM1
9. B2B connector Samtec Razor Beam™ LSHM-150, JM2
10. B2B connector Samtec Razor Beam™ LSHM-130, JM3
11. 4 GByte eMMC memory, U6
12. Lattice Semiconductor MachXO2 System Controller CPLD, U21
13. I²C programmable, any  frequency , any output  quad clock generator, U10
14. Highly integrated full featured hi-speed USB 2.0 ULPI transceiver, U18
15. LED D1(Red) Done Pin
16. LED D2 (Green) CPLD Status, User LED
    
17. LED D3 (Red) PS Error
    
18. LED D4 (Green) PS Error Status
    

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.

Table 2: Boot mode pin description

For more information refer to the TE0820 CPLD - BootMode section. 

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Zynq MPSoC's I/O banks signals connected to the B2B connectors:

Table 3: General overview of board to board I/O signals

For detailed information about the pin-out, please refer to the Pin-out table.

MGT Lanes

The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 4: MGT lanes

There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

Table 5: MGT reference clock sources

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.

Table 6: JTAG interface signals

Pin 89 JTAGEN of B2B connector JM1 is used to control which device is accessible via JTAG. If set to low or grounded, JTAG interface will be routed to the Xilinx Zynq MPSoC. If pulled high, JTAG interface will be routed to the System Controller CPLD.

System Controller CPLD I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Table 7: System Controller CPLD special purpose pins.

See also

• 4 x 5 SoM Integration Guide#4x5SoMIntegrationGuide-4x5ModuleControllerIOs
• TE0820 CPLD
• TE0820-REV01_REV02 CPLD

Default PS MIO Mapping

Table 8: TE0820-03 PS MIO mapping

Gigabit Ethernet

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.

Ethernet PHY connection

Table 9: General overview of the Gigabit Ethernet PHY signals

USB Interface

USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 25.000000 MHz oscillator (U15).

USB PHY connection

Table 10: General overview of the USB PHY signals.

I2C Interface

On-board I²C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I²C1 by default. Addresses for on-board I²C slave devices are listed in the table below:

Table 11: Address table of the I²C bus slave devices.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U21) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

See also TE0820 System Controller CPLD page.

eMMC Flash Memory

eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips MTFC4GACAJCN-4M IT (FLASH - NAND Speicher-IC 32 Gb (4 G x 8) MMC ) is used.

DDR4 Memory

By default TE0820-03 module has two 16-bit wide Samsung K4A8G165WB DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 2 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

Two quad SPI compatible serial bus flash N25Q512A memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U21).

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U25) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x50.

Programmable Clock Generator

There is a Silicon Labs I²C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I²C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks. It is possible to use the clocks connected to the GTR bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.

Once running, the frequency and other parameters can be changed by programming the device using the I²C bus connected between the FPGA (master) and clock generator (slave). For this, proper I²C bus logic has to be implemented in FPGA.

Table 12: General overview of the on-board quad clock generator I/O signals

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table 13: Reference clock signals

On-board LEDs

Table 14: On-board LEDs

Power and Power-on Sequence

Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

Table 15: Power consumption

 * TBD - To Be Determined soon with reference design setup.

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power Distribution Dependencies

See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0820 module.

Power-On Sequence

The TE0820 SoM meets the recommended criteria to power up the Xilinx Zynq chip properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

For highest efficiency of the on-board DC-DC regulators, it is recommended to use one 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, indicating that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.

Power Rails

Table 16: TE0820-03 power rails

Bank Voltages

Table 17: TE0820-03 I/O bank voltages

See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

Board to Board Connectors

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Table 18: Module absolute maximum ratings

Recommended Operating Conditions

Table 19: Recommended operating conditions

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8 mm

• PCB thickness: 1.6 mm

• Highest part on PCB: approximately 5 mm. Please download the step model for exact numbers.

All dimensions are shown in millimeters.

Revision History

Hardware Revision History

Table 20: Hardware revision history table

Document Change History

v.74

Table 21: Document change history

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